Patent application number | Description | Published |
20080221004 | Cleaning Solution for a Semiconductor Wafer - A cleaning solution for a semiconductor wafer comprises ammonia, hydrogen peroxide, a complexing agent and a block copolymer surfactant diluted in water. The cleaning solution can be used in single wafer cleaning tools to remove both particulate contaminants and metallic residues. | 09-11-2008 |
20080271274 | Apparatus for Cleaning of Circuit Substrates - Silicon wafers and the like are cleaned using new scrubber-type apparatus in which measures are taken to compensate for differential cleaning of the central region of the wafer by: using rotary brushes having one or more non-contact portions arranged in the section thereof that faces the central region of the substrate, or toggling the relative position of the wafer and the rotary brushes, or directing cleaning fluid(s) preferentially towards the central region of the wafer. Another aspect of the invention provides scrubber-type cleaning apparatus in which the rotary brushes are replaced by rollers ( | 11-06-2008 |
20080282778 | Method For Testing a Slurry Used to Form a Semiconductor Device - A method for forming a semiconductor device, the method includes providing a semiconductor substrate, applying a slurry to the semiconductor substrate, wherein the slurry was tested using a testing method includes taking a first undiluted sample from a top of the slurry; determining a first particle size distribution characteristic of the first undiluted sample; taking a second undiluted sample from a bottom of the slurry; determining a second particle size distribution characteristic of the second undiluted sample; and comparing a difference between the first particle size distribution characteristic and the second particle size distribution characteristics with a first predetermined value. | 11-20-2008 |
20090045164 | "UNIVERSAL" BARRIER CMP SLURRY FOR USE WITH LOW DIELECTRIC CONSTANT INTERLAYER DIELECTRICS - During processing of a semiconductor wafer bearing a structure including a low-k dielectric layer, a cap layer and the metal-diffusion barrier layer, a chemical mechanical polishing method applied to remove the metal-diffusion barrier material involves two phases. In the second phase of the barrier-CMP method, when the polishing interface is close to the low-k dielectric material, the polishing conditions are changed so as to be highly selective, producing a negligible removal rate of the low-k dielectric material. The polishing conditions can be changed in a number of ways including: changing parameters of the composition of the barrier slurry composition, and mixing an additive into the barrier slurry. | 02-19-2009 |
20090115031 | SEMICONDUCTOR DEVICE INCLUDING A COUPLED DIELECTRIC LAYER AND METAL LAYER, METHOD OF FABRICATION THEREOF, AND PASSIVATING COUPLING MATERIAL COMPRISING MULTIPLE ORGANIC COMPONENTS FOR USE IN A SEMICONDUCTOR DEVICE - A material for passivating a dielectric layer in a semiconductor device has a molecular structure permitting or at least promoting liquid phase metal deposition thereon in a subsequent process step. The contemplated material may be constituted by multiple organic components. A semiconductor device including a layer of the passivating coupling material, and a method of manufacturing such a semiconductor device are also contemplated. | 05-07-2009 |
20090301867 | INTEGRATED SYSTEM FOR SEMICONDUCTOR SUBSTRATE PROCESSING USING LIQUID PHASE METAL DEPOSITION - A system for processing a semiconductor substrate during fabrication of semiconductor devices provides a plurality of semiconductor substrate processing stations in a physically integrated system, as well as a semiconductor substrate transport system for transporting a semiconductor substrate between the respective processing stations. In particular, the processing system according to the present invention favors the use of liquid phase process steps, particularly deposition process steps, instead of gas or vapor phase processing. Even more particularly, the system contemplates deposition of a metallic barrier layer | 12-10-2009 |
20100273330 | RINSE FORMULATION FOR USE IN THE MANUFACTURE OF AN INTEGRATED CIRCUIT - The present invention relates to a solution for treating a surface of a substrate for use in a semiconductor device. More particularly, the present invention relates to a liquid rinse formulation for use in semiconductor processing, wherein the liquid formulation contains: i. a surface passivation agent; and ii. an oxygen scavenger, wherein the pH of the rinse formulation is 8.0 or greater. | 10-28-2010 |
20110021024 | SURFACE TREATMENT IN SEMICONDUCTOR MANUFACTURING - The present invention provides a process for forming a capping layer on a conducting interconnect for a semiconductor device, the process comprising: providing a substrate comprising one or more conductors in a dielectric layer, the conductors having an oxide layer at their surface; exposing the surface of the substrate to a vapour of β-diketone or a β-ketoimine; and depositing a capping layer on the surface of at least some of the one or more conductors. The present invention further provides an apparatus for carrying out this method. | 01-27-2011 |