Patent application number | Description | Published |
20090260796 | Passive Cooling In Response To Ambient Environmental Properties - A system for passively cooling an electronic component includes a conduit configured to carry a pressurized cooling fluid. The conduit has a plurality of delivery orifices configured to dispense the pressurized cooling fluid from the conduit to cool the electronic component. Each delivery orifice has a hydrogel mechanism associated therewith, which is configured to individually control each of the plurality of delivery orifices to automatically regulate flow of the cooling fluid in response to a variation in a property of an ambient environment surrounding the hydrogel mechanism. The property of the ambient environment is influenced by an operation of the electronic component. | 10-22-2009 |
20110253966 | IONIC-MODULATED DOPANT PROFILE CONTROL IN NANOSCALE SWITCHING DEVICES - A nanoscale switching device is provided, comprising: a first electrode of a nanoscale width; a second electrode of a nanoscale width; an active region disposed between the first and second electrodes, the active region having at least one non-conducting layer comprising an electronically semiconducting or nominally insulating and a weak ionic conductor switching material capable of carrying a species of dopants and transporting the dopants under an electric field; and a source layer interposed between the first electrode and the second electrode and comprising a highly reactive and highly mobile ionic species that reacts with a component in the switching material to create dopants that are capable of drifting through the non-conducting layer under an electric field, thereby controlling dopant profile by ionic modulation. A crossbar array comprising a plurality of the nanoscale switching devices is also provided, along with a process for making at least one nanoscale switching device. | 10-20-2011 |
20120081945 | MEMORY ARRAY WITH GRADED RESISTANCE LINES - A memory array with graded resistance lines includes a first set of lines intersecting a second set of lines. A line from one of the sets of lines includes a graded resistance along a length of the line. | 04-05-2012 |
20120112167 | NANOSCALE ELECTRONIC DEVICE - One example of the present invention is a nanoscale electronic device comprising a first conductive electrode, a second conductive electrode, and an anisotropic dielectric material layered between the first and second electrodes having a permittivity in a direction approximately that of the shortest distance between the first and second electrodes less than the permittivity in other directions within the anisotropic dielectric material. Additional examples of the present invention include integrated circuits that contain multiple nanoscale electronic devices that each includes an anisotropic dielectric material layered between first and second electrodes having a permittivity in a direction approximately that of the shortest distance between the first and second electrodes less than the permittivity in other directions within the anisotropic dielectric material. | 05-10-2012 |
20130009128 | NANOSCALE SWITCHING DEVICE - A nanoscale switching device has an active region containing a switching material. The switching device has a first electrode and a second electrode with nanoscale widths, and the active region is disposed between the first and second electrodes. A protective cladding layer surrounds the active region. The protective cladding layer is formed of a cladding material unreactive to the switching material. An interlayer isolation layer formed of a dielectric material is disposed between the first and second electrodes and outside the protective cladding layer. | 01-10-2013 |
20130114329 | Multilayer Memory Array - A multilayer crossbar memory array includes a number of layers. Each layer includes a top set of parallel lines, a bottom set of parallel lines intersecting the top set of parallel lines, and memory elements disposed at intersections between the top set of parallel lines and the bottom set of parallel lines. A top set of parallel lines from one of the layers is a bottom set of parallel lines for an adjacent one of the layers. | 05-09-2013 |
20130168629 | NANOSCALE SWITCHING DEVICE - A nanoscale switching device comprises a first electrode of a nanoscale width; a second electrode of a nanoscale width; an active region disposed between the first and second electrodes, the active region containing a switching material; an area within the active region that constrains current flow between the first electrode and the second electrode to a central portion of the active region; and an interlayer dielectric layer formed of a dielectric material and disposed between the first and second electrodes outside the active region. A nanoscale crossbar array and method of forming the nanoscale switching device are also disclosed. | 07-04-2013 |
20140027700 | MEMRISTOR WITH EMBEDDED SWITCHING LAYER - A method of making a memristor having an embedded switching layer include exposing a surface portion of a first electrode material within a via to a reactive species to form the switching layer embedded within and at surface of the via. The via is in contact with a first conductor trace. The method further includes depositing a layer of a second electrode material adjacent to the via surface and patterning the layer into a column aligned with the via. The method further includes depositing an interlayer dielectric material to surround the column and providing a second conductor trace in electrical contact with the second electrode material of the column. | 01-30-2014 |
20140097398 | MEMRISTIVE DEVICES AND MEMRISTORS WITH RIBBON-LIKE JUNCTIONS AND METHODS FOR FABRICATING THE SAME - Memristive devices, memristors and methods for fabricating memristive devices are disclosed. In one aspect, a memristor includes a first electrode wire and a second electrode wire. The second electrode wire and the first electrode wire define an overlap area. The memristor includes an electrode extension in contact with the first electrode wire and disposed between the first and second electrode wires. At least one junction is disposed between the second electrode wire and the electrode extension. Each junction contacts a portion of the electrode extension and has a junction contact area with the second electrode wire, and the sum total junction contact area of the at least one junction is less than the overlap area. | 04-10-2014 |
20140211535 | MITIGATION OF INOPERABLE LOW RESISTANCE ELEMENTS IN PROGRAMABLE CROSSBAR ARRAYS - A programmable crossbar array includes a layer of row conductors and a layer of column conductors with the row conductors crossing over the column conductors to form junctions. Programmable crosspoint devices are sandwiched between a row conductor and a column conductor at a junction. Each programmable crosspoint device includes a data element with a first programming threshold and a control element with a second programming threshold, in which the second programming threshold is greater than the first programming threshold. A method for mitigating shorts in a programmable crossbar array is also provided. | 07-31-2014 |
20140313816 | SELECT DEVICE FOR CROSS POINT MEMORY STRUCTURES - The present disclosure provides a memory cell that includes a resistive memory element disposed between a first conductor and a second conductor, the first conductor and the second conductor configured to activate the resistive memory element. The memory cell also includes a backward diode disposed in series with the memory element between the memory element and either the first conductor or the second conductor. | 10-23-2014 |