Jang, Singapore
Deck Chun Jang, Singapore SG
Patent application number | Description | Published |
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20120260752 | ASSEMBLY AND METHOD FOR IC UNIT ENGAGEMENT - A picker assembly includes a plurality of pickers in selective variable spaced relation, a shaft having a plurality of cam plates, the cam plates co-axial with said shaft and having a variable thickness. The cam plates are in engagement with the pickers and positioned in interstitial spaces between the pickers. The selective variability in spacing is provided by rotation of the shaft such that thickness variation of the cam plates move the respective pickers along an axis parallel to the shaft. | 10-18-2012 |
Deok Chun Jang, Singapore SG
Patent application number | Description | Published |
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20120184086 | PUNCH SINGULATION SYSTEM AND METHOD - A punching system for singulating IC units comprising: a punching assembly arranged to receive a substrate and singulate said substrate into the IC units; a rotary carrier rotatable from a first position to a second position said rotary carrier arranged to receive said units at the first position and carry said units to the second position through rotation; wherein said rotary carrier includes recesses for receiving at least a portion of the units. A punching assembly comprising a die block having recesses for receiving selectively replaceable inserts wherein said inserts correspond to a punch pattern specific to a predetermined IC package arrangement. | 07-19-2012 |
20130008836 | METHOD AND APPARATUS FOR IMPROVED SORTING OF DICED SUBSTRATES - A method for inspecting and sorting a plurality of IC units comprising the steps of: delivering a frame containing said IC units to a unit picking station; conducting a first inspection of said units during the delivering step and recording the subsequent result; removing said units from the frame, and moving said units from the unit picking station to a flipping station; conducting a second inspection of said units during the moving step and recording the subsequent result; flipping said units to expose an opposed face said units; conducting a third inspection of said opposed face and recording the subsequent result, then; sorting said units into categories based on the recorded results from the first, second and third inspecting steps. | 01-10-2013 |
20130209205 | SYSTEM AND METHOD FOR OFFLOADING IC UNITS - A shuttle table assembly comprising a shuttle table for receiving a plurality of IC units at a first position and for offloading said units at a second position, said shuttle table movable from said first to second position; a cover assembly mounted to said shuttle table, the cover assembly having at least one cover movable from an open position to a closed position, said closed position covering said units on the shuttle table; wherein the cover assembly is coupled to a guide for closing the cover as the shuttle table moves from the first to the second position. | 08-15-2013 |
In Cheol Jang, Singapore SG
Patent application number | Description | Published |
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20150074847 | ENHANCING PROTEIN STABILITY IN TRANSGENIC PLANTS - The present invention provides compositions and methods for enhancing protein stability in transgenic plants. The compositions are nucleic acid constructs which encode fusion proteins, fusion proteins, transgenic plant cells and transgenic plants. A fusion protein in accordance with the present invention comprises a protein of interest and a UBA1 or UBA2 domain of an | 03-12-2015 |
Taehoan Jang, Singapore SG
Patent application number | Description | Published |
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20090079069 | Semiconductor Device and Method of Forming Interconnect Structure in Non-Active Area of Wafer - A semiconductor wafer includes a plurality of semiconductor die. Contact pads are formed on an active area of the semiconductor die and non-active area of the semiconductor wafer between the semiconductor die. Solder bumps are formed on the contact pads in both the active area of the semiconductor die and non-active area of the semiconductor wafer between the semiconductor die. The I/O terminal count of the semiconductor die is increased by forming solder bumps in the non-active area of the wafer. An encapsulant is formed over the solder bumps. The encapsulant provides structural support for the solder bumps formed in the non-active area of the semiconductor wafer. The semiconductor wafer undergoes grinding after forming the encapsulant to expose the solder bumps. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is mounted to a package substrate with solder paste or socket. | 03-26-2009 |
Tae Hoan Jang, Singapore SG
Patent application number | Description | Published |
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20090127719 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PACKAGE SUBSTRATE HAVING CORNER CONTACTS - A integrated circuit package system includes: forming a package substrate with a top substrate side and a bottom substrate side; forming a corner contact in a first corner of the bottom substrate side, the corner contact extending to a substrate edge of the package substrate; mounting an integrated circuit device over the top substrate side; connecting an electrical interconnect between the integrated circuit device and the top substrate side; and forming a package encapsulation over the top substrate side, the integrated circuit device, and the electrical interconnect. | 05-21-2009 |
20100052150 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PACKAGE SUBSTRATE HAVING CORNER CONTACTS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit package system includes: forming a package substrate with a top substrate side and a bottom substrate side; forming a corner contact in a first corner of the bottom substrate side, the corner contact extending to a substrate edge of the package substrate; mounting an integrated circuit device over the top substrate side; connecting an electrical interconnect between the integrated circuit device and the top substrate side; and forming a package encapsulation over the top substrate side, the integrated circuit device, and the electrical interconnect. | 03-04-2010 |
20100244239 | Semiconductor Device and Method of Forming Enhanced UBM Structure for Improving Solder Joint Reliability - A semiconductor device has a first conductive layer formed over a substrate. A first insulating layer is formed over the first conductive layer. A second conductive layer is formed over first insulating layer and first conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. An under bump metallization layer (UBM) is formed over the third insulating layer and second conductive layer. A UBM build-up structure is formed over the UBM. The UBM build-up structure has a sloped sidewall and is confined within a footprint of the UBM. The UBM build-up structure extends above the UBM to a height of 2-20 micrometers. The UBM build-up structure is formed in sections occupying less than an area of the UBM. A solder bump is formed over the UBM and UBM build-up structure. The sections of the UBM build-up structure provide exits for flux vapor escape. | 09-30-2010 |