Jang, Asan-Si
Eun-Je Jang, Asan-Si KR
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20120008059 | LIQUID CRYSTAL DISPLAY - A liquid crystal display includes first and second gate lines and first and second data lines, on a first substrate, a first thin film transistor connected to the first gate and data lines and including a first source and drain electrode, a second thin film transistor connected to the second gate and data lines and including a second source and drain electrode, first and second pixel electrodes contacting a portion of the first and second drain electrodes, respectively, a passivation layer on the first and second pixel electrodes and the first and second thin film transistors, and a reference electrode on a passivation layer and overlapping the first pixel electrode and the second pixel electrode. The reference electrode includes a plurality of branch electrodes. The first thin film transistor is right of the first data line and the second thin film transistor is left of the second data line. | 01-12-2012 |
20120013815 | LIQUID CRYSTAL DISPLAY AND MANUFACTURING METHOD THEREOF - A liquid crystal display includes an insulation substrate; a gate line, a gate electrode, and a reference voltage line positioned on the insulation substrate; a reference electrode contacting the reference voltage line; a gate insulating layer disposed on the gate line and the reference electrode; a semiconductor disposed on the gate insulating layer and positioned on the gate electrode; a data line and a drain electrode disposed on the semiconductor; a passivation layer disposed on the data line and the drain electrode; and a pixel electrode connected to the drain electrode and overlapping the reference electrode. | 01-19-2012 |
20140016058 | LIQUID CRYSTAL DISPLAY - A liquid crystal display includes first and second gate lines and first and second data lines, on a first substrate, a first thin film transistor connected to the first gate and data lines and including a first source and drain electrode, a second thin film transistor connected to the second gate and data lines and including a second source and drain electrode, first and second pixel electrodes contacting a portion of the first and second drain electrodes, respectively, a passivation layer on the first and second pixel electrodes and the first and second thin film transistors, and a reference electrode on a passivation layer and overlapping the first pixel electrode and the second pixel electrode. The reference electrode includes a plurality of branch electrodes. The first thin film transistor is right of the first data line and the second thin film transistor is left of the second data line. | 01-16-2014 |
Hyun-Hun Jang, Asan-Si KR
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20150101166 | POLARIZING FILM CUTTING KNIFE AND METHOD OF MANUFACTURING POLARIZING PLATE USING THE SAME - A polarizing film cutting knife includes a body portion extending in a first direction, and a knife portion connected to the body portion. The knife portion includes a first surface and a second surface. The first and second surfaces form a first angle. The first angle is about 21.8 to 22.2 degrees. | 04-16-2015 |
Jae Won Jang, Asan-Si KR
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20150235884 | CEILING STORAGE DEVICE CAPABLE OF WAFER PURGING - The invention provides an apparatus for stocking and purging a wafer at a ceiling. The apparatus includes: a rail that is formed so as to be installed on a ceiling to guide a vehicle; a stock system that is formed so as to be installed on the ceiling and is formed so as to receive a container, which contains wafers, from the vehicle and stock the container; and a purge assembly that is installed so as to communicate with the container through the stock system and is formed so as to purge the wafers, which are contained in the container, with gas. | 08-20-2015 |
Jin-Gwan Jang, Asan-Si KR
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20150116307 | DC-DC CONVERTER, DISPLAY APPARATUS HAVING THE SAME AND METHOD OF DRIVING DISPLAY PANEL USING THE SAME - A method of differently producing driving clock signals for a shift register of a gate lines driving circuit of a Liquid Crystal Display (LCD), the method includes the steps of determining whether an ambient temperature is greater than or not in comparison to a predetermined threshold temperature; in response to the determining indicating that the ambient temperature is greater, using a first ON voltage and a first charge canceling method; and in response to the determining indicating that the ambient temperature is not greater, using a second ON voltage and a second charge canceling method, where the second ON voltage is different from the first ON voltage and where the second charge canceling method is different from the first charge canceling method. The second charge canceling method may have a shorter duration than that of the first charge canceling method. The second ON voltage may be greater than the first ON voltage. | 04-30-2015 |
Jinsic Jang, Asan-Si KR
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20160034203 | Storage Device, Memory Card, And Communicating Method Of Storage Device - A storage device includes a host interface configured to communicate with a host device according to a first protocol through an input terminal, an output terminal, and a clock terminal. The input terminal is configured to receive an input signal from the host device according to the first protocol. The output terminal is configured to output an output signal to the host device according to the first protocol. The clock terminal configured to receive a clock signal from the host device according to the first protocol. The host interface is configured to communicate with the host device according to a second protocol through the clock terminal, the second protocol being different from the first protocol. | 02-04-2016 |
Jinwon Jang, Asan-Si KR
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20160109755 | DISPLAY DEVICE - A display device includes: a curved display panel; at least one light source module configured to provide light to the display panel; a bottom case configured to accommodate the light source module; and at least one signal transmission unit connected to an end portion of the light source module, the signal transmission unit including at least one driving line transmitting a driving signal to the light source module and at least one base line transmitting a base signal. | 04-21-2016 |
Jin-Wook Jang, Asan-Si KR
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20160086898 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package includes a wiring substrate including a plurality of solder pads; a chip including a plurality of chip pads connected to the solder pads through a plurality of solders; a sealing layer configured to seal the chip and the solders, at least one void being between the solders; and a solder extrusion prevention layer on one sidewall of the solder exposed by the at least one void. | 03-24-2016 |
Jongkak Jang, Asan-Si KR
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20110171338 | APPARATUS AND METHOD FOR MOLDING COMPOUND - Provided are a device and method for molding a compound. The device for molding a compound may include a lower mold, an upper mold, and a cull degating unit. The lower mold may be configured to support a substrate and attach to a compound injector and the upper mold may be configured to cover the lower mold to form a space between the lower mold and the upper mold for receiving a compound from the compound injector. The cull degating unit may be in the upper mold and the cull degating unit may be configured to separate a cull of the compound in an injection passage from the compound molded on the substrate. The compound injector may be configured to inject a compound into the device such that a least a portion of the compound is molded on the substrate. | 07-14-2011 |
Kyoung-Jun Jang, Asan-Si KR
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20090189679 | GATE DRIVING CIRCUIT AND DISPLAY APPARATUS HAVING THE SAME - A gate driving circuit includes cascaded stages, each including a pull-up part, a carry part, a pull-up driving part, a holding part and an inverter. The pull-up part pulls up a gate voltage to an input clock. The carry part pulls up a carry voltage to the input clock. The pull-up driving part is connected to a control terminal (Q-node) common to the carry part and the pull-up part, and receives a previous carry voltage from a previous stage to turn on the pull-up part and the carry part. The holding part holds the gate voltage at an off-voltage, and the inverter controls at least one of turning on the holding part and turning off the holding part based on an inverter clock. A high level of the inverter clock in a given horizontal period (1H) temporally precedes a high level of the input clock by a predetermined time interval. | 07-30-2009 |
Ungjin Jang, Asan-Si KR
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20150058685 | METHOD AND SYSTEM OF TESTING SEMICONDUCTOR MEMORY - A method of testing a semiconductor memory includes generating a logical value of a test pattern through an algorithm pattern generator included in a field programmable gate array. The generated logical value is programmed in a DUT under the control of a DQ signal responding to a DQ enable signal that is generated from automatic test equipment and is then transferred to the field programmable gate array. The programmed logical value is captured from the DUT under the control the DQ signal. The generated logical value is compared with the captured logical value. Whether the DUT is defective is determined according to a result of the comparison. The DQ enable signal is applied to a time point different from a time point when a SYNC clock for synchronizing the automatic test equipment with the field programmable gate array is applied. | 02-26-2015 |
Yong Chul Jang, Asan-Si KR
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20160091531 | TEST BOARD, TEST SYSTEM INCLUDING THE SAME, AND MANUFACTURING METHOD THEREOF - Provided is a test board including a main board which is configured to be connected to a plurality of devices-under-test (DUTs) and includes a plurality of test signal paths for transmitting a plurality of test signals input from an external tester to pins of at least one of the DUTs or transmitting a test result from the DUT to the tester, and a farm board which is connected to the main board and configured to mount therein a plurality of passive elements which are configured to be connected to at least one of the pins of the DUT through at least one of the test signal paths of the main board, when a test operation is performed, thereby improving a power integrity property or a signal integrity property in the test operation. | 03-31-2016 |
Younghwan Jang, Asan-Si KR
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20150285748 | EXAMINATION APPARATUS, METHOD OF EXAMINING SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF ELECTRONIC DEVICE - Provided are an examination apparatus and a method of examining a semiconductor device. The examination apparatus includes a support on which a semiconductor device to be examined is disposed, a light irradiation unit that obliquely emits light at a set angle to the support, an image capturing member configured to capture an image of an upper surface of the support, and a control member configured to determine, based on the image captured by the image capturing member, whether a height of the semiconductor device is standard by using the set angle and an examination pattern formed on the semiconductor device by the light. | 10-08-2015 |