Patent application number | Description | Published |
20080209129 | Cache with High Access Store Bandwidth - A cache memory system and method for supporting multiple simultaneous store operations using a plurality of tag memories is provided. The cache data system further provides a plurality of multiple simultaneous cache store functions along with a single cache load function that is simultaneous with the store functions. Embodiments create a cache memory wherein the cache write buffer does not operate as a bottle neck for data store operations into a cache memory system or device. | 08-28-2008 |
20090217004 | CACHE WITH PREFETCH - A prefetch bit ( | 08-27-2009 |
20100005274 | VIRTUAL FUNCTIONAL UNITS FOR VLIW PROCESSORS - A virtual functional unit design is presented that is employed in a statically scheduled VLIW processor “Virtual” views of the function unit appear to the processor scheduler that exceed the number of physical instantiations of the functional unit. As a result, significant processor performance improvements can be achieved for those types of functional units that are too difficult or too costly to physically duplicate. By providing different virtual views to the different clusters of a VLIW processor, the compiler/scheduler can generate more efficient code for the processor, than a processor without virtual views and the physical unit restricted to a subset of the processor's clusters. The compiler/scheduler guarantees that the restrictions with respect to scheduling of operations for functional units with multiple virtual views is met. NON-clustered processors also benefit from virtual views. By providing multiple virtual views in multiple issue slots of a physical function unit, the compiler/scheduler has more freedom to schedule operations for the functional unit. | 01-07-2010 |
20100050164 | PIPELINED PROCESSOR AND COMPILER/SCHEDULER FOR VARIABLE NUMBER BRANCH DELAY SLOTS - Different numbers of delay slots are assigned by a compiler/scheduler to each different type of jump operation in a pipelined processor system. The number of delay slots is variable and kept to the minimum needed by each type of jump operation. A compatible processor uses a corresponding number of branch delay slots to exploit the difference in predictability of different types of branch or jump operations. Different types of jump operations resolved their target addresses in different numbers of delay slots. As a result, the compiler/scheduler is able to generate more efficient code than for a processor with a fixed number of delay slots for all jump types, resulting in better processor performance. | 02-25-2010 |
20100077151 | HARDWARE TRIGGERED DATA CACHE LINE PRE-ALLOCATION - A computer system includes a data cache supported by a copy-back buffer and pre-allocation request stack. A programmable trigger mechanism inspects each store operation made by the processor to the data cache to see if a next cache line should be pre-allocated. If the store operation memory address occurs within a range defined by START and END programmable registers, then the next cache line that includes a memory address within that defined by a programmable STRIDE register is requested for pre-allocation. Bunches of pre-allocation requests are organized and scheduled by the pre-allocation request stack, and will take their turns to allow the cache lines being replaced to be processed through the copy-back buffer. By the time the processor gets to doing the store operation in the next cache line, such cache line has already been pre-allocated and there will be a cache hit, thus saving stall cycles. | 03-25-2010 |
20100271084 | SOUCE-SYNCHRONOUS DATA LINK FOR SYSTEM-ON-CHIP DESIGN - A method of producing an integrated circuit ( | 10-28-2010 |
20100274974 | SYSTEM AND METHOD FOR REPLACING DATA IN A CACHE - A system and method for replacing data in a cache utilizes cache block validity information, which contains information that indicates that data in a cache block is no longer needed for processing, to maintain least recently used information of cache blocks in a cache set of the cache, identifies the least recently used cache block of the cache set using the least recently used information of the cache blocks in the cache set, and replaces data in the least recently used cache block of the cache set with data from main memory. | 10-28-2010 |
20110051802 | SYSTEM AND METHOD FOR VIDEO COMPRESSION USING NON-LINEAR QUANTIZATION AND MODULAR ARITHMETIC COMPUTATION - A system and method for video compression utilizes non-linear quantization and modular arithmetic computation to perform differential coding on multiple blocks of video data and uses a result of the differential coding to generate a codeword. | 03-03-2011 |
20140022185 | INTERFACE AND SYNCHRONIZATION METHOD BETWEEN TOUCH CONTROLLER AND DISPLAY DRIVER FOR OPERATION WITH TOUCH INTEGRATED DISPLAYS - Apparatuses and methods of synchronizing a display driver integrated circuit (DDI) and a touch screen controller (TSC) integrated circuit that are coupled to a display integrated touch panel, such as an in-cell panel, and allowing multi-phase transmit (TX) scanning of the in-cell touch panel. One apparatus includes a DDI configured to receive signals on a video interface from a host processor over a video interface and to drive electrodes of a touch panel. The DDI is configured to receive control signals from a TSC over a control interface to drive different transmit (TX) phase sequences of a TX signal in different sensing interval on the electrodes of the touch panel. | 01-23-2014 |
20140022206 | HARDWARE ACCELERATOR FOR TOUCHSCREEN DATA PROCESSING - A contact's interaction with a sensing array is subject to several external and internal stimuli which may impact a processing unit's confidence in the characteristics of that interaction or the presence of the interaction itself. Fidelity of user action is greatly improved with a step-wise and holistic analysis of a contact on an array of capacitance sensors, which allows for repetition of certain steps of processing or the entire operation if threshold confidence levels are not achieved. | 01-23-2014 |
20140022211 | TOUCHSCREEN DATA PROCESSING - Capacitive touch sensors and touchscreen data processing methods are provided. In one embodiment, the method includes sequentially integrating and converting charge from each of a plurality of sensing capacitors in an array to digital data, the digital data including sample values corresponding to a measured capacitance for each of the plurality of sensing capacitors. Noise is then separated from useful information by filtering the sample values on a sample-by-sample basis. Finally, the filtered sample values are summed and a position of at least one contact on the array determined using the filtered capacitance values. Other embodiments are also provided. | 01-23-2014 |
20140347320 | INTERFACE AND SYNCHRONIZATION METHOD BETWEEN TOUCH CONTROLLER AND DISPLAY DRIVER FOR OPERATION WITH TOUCH INTEGRATED DISPLAYS - Apparatuses and methods of synchronizing a display driver integrated circuit (DDI) and a touch screen controller (TSC) integrated circuit that are coupled to a display integrated touch panel, such as an in-cell panel, and allowing multi-phase transmit (TX) scanning of the in-cell touch panel. One apparatus includes a DDI configured to receive signals on a video interface from a host processor over a video interface and to drive electrodes of a touch panel. The DDI is configured to receive control signals from a TSC over a control interface to drive different transmit (TX) phase sequences of a TX signal in different sensing interval on the electrodes of the touch panel. | 11-27-2014 |