| Patent application number | Description | Published |
|---|
| 20080217653 | Method of Manufacturing a Semiconductor Device with an Isolation Region and a Device Manufactured by the Method - A method of manufacturing a semiconductor device includes forming trench isolation structures, exposing some of the trench isolation structures | 09-11-2008 |
| 20080261358 | Manufacture of Lateral Semiconductor Devices - A method of manufacturing a lateral semiconductor device comprising a semiconductor body ( | 10-23-2008 |
| 20080296694 | Semiconductor Device with Field Plate and Method - A method of making a semiconductor device includes forming shallow trench isolation structures ( | 12-04-2008 |
| 20090008566 | GEIGER MODE AVALANCHE PHOTODIODE - A avalanche mode photodiode array ( | 01-08-2009 |
| 20090053872 | METHOD OF MANUFACTURING A BIPOLAR TRANSISTOR - The invention relates to a method of manufacturing a bipolar transistor on a semiconductor substrate ( | 02-26-2009 |
| 20090072319 | SEMICONDUCTOR DEVICE WITH RELATIVELY HIGH BREAKDOWN VOLTAGE AND MANUFACTURING METHOD - A semiconductor device includes at least one active component ( | 03-19-2009 |
| 20090072351 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE OBTAINED BY MEANS OF SAID METHOD - The invention relates to a method of manufacturing a semiconductor device ( | 03-19-2009 |
| 20090127615 | Semiconductor device and method for manufacture - A semiconductor device is formed by forming a second trench | 05-21-2009 |
| 20090209092 | SEIMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE THEREOF - A FinFET and methods for its manufacture are provided. The method of the invention provides an elegant process for manufacturing FinFETs with separated gates. It is compatible with a wide range of dielectric materials and gate electrode materials, providing that the gate electrode material(s) can be deposited conformally. Provision of at least one upstanding structure (or “dummy fin”) ( | 08-20-2009 |
| 20090278186 | Double Gate Transistor and Method of Manufacturing Same - A double gate transistor on a semiconductor substrate ( | 11-12-2009 |
| 20090302375 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND DEVICE MANUFACTURED BY THE METHOD - A method of manufacturing a semiconductor device includes forming trenches ( | 12-10-2009 |
| 20100014631 | SCINTILLATOR BASED X-RAY SENSITIVE INTEGRATED CIRCUIT ELEMENT WITH DEPLETED ELECTRON DRIFT REGION - It is described an integrated circuit design and a method to fabricate the same for a high-efficiency, low-noise, position sensitive X-ray detection in particular for medical applications. The device ( | 01-21-2010 |
| 20100044760 | SELF-ALIGNED IMPACT-IONIZATION FIELD EFFECT TRANSISTOR - An impact ionisation MOSFET is formed with the offset from the gate to one of the source/drain regions disposed vertically within the device structure rather than horizontally. The semiconductor device comprises a first source/drain region having a first doping level; a second source/drain region having a second doping level and of opposite dopant type to the first source/drain region, the first and second source/drain regions being laterally separated by an intermediate region having a doping level less than either of the first and second doping levels; a gate electrode electrically insulated from, and disposed over, the intermediate region, the first and second source/drain regions being laterally aligned with the gate electrode; where the entire portion of the first source/drain region that forms a boundary with the intermediate region is separated vertically from the top of the intermediate region. | 02-25-2010 |
| 20100213517 | HIGH VOLTAGE SEMICONDUCTOR DEVICE - This invention describes implementation of medium/high voltage semiconductor devices with a better voltage-blocking capability versus specific on-resistanσe trade off. This approach can be implemented in baseline and submicron CMOS without any additional process steps. Said devices comprise dielectric regions and semiconductor regions formed between them. Conductive extentions are formed on the dielectric regions, said extentions interacting capacitively with the semiconducter regions. | 08-26-2010 |
| 20100237434 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SUCH A DEVICE - The invention relates to a semiconductor device ( | 09-23-2010 |
| 20100244125 | POWER SEMICONDUCTOR DEVICE STRUCTURE FOR INTEGRATED CIRCUIT AND METHOD OF FABRICATION THEREOF - A power semiconductor device comprises a conductive gate, provided in an upper part of a trench ( | 09-30-2010 |
| 20100314684 | FINFET WITH SEPARATE GATES AND METHOD FOR FABRICATING A FINFET WITH SEPARATE GATES - The present invention relates to a FinFET with separate gates and to a method for fabricating the same. A dielectric gate-separation layer between first and second gate electrodes has an extension in a direction pointing from a first to a second gate layer that is smaller than a lateral extension of the fin between its opposite lateral faces. This structure corresponds with a processing method that starts from a covered basic FinFET structure with a continuous first gate layer, and proceeds to remove parts of the first gate layer and of a first gate-isolation layer through a contact opening to the gate layer. Subsequently, a replacement gate-isolation layer that at the same time forms the gate separation layer fabricated, followed by filling the tunnel with a replacement gate layer and a metal filling. | 12-16-2010 |
| 20110006369 | FINFET TRANSISTOR WITH HIGH-VOLTAGE CAPABILITY AND CMOS-COMPATIBLE METHOD FOR FABRICATING THE SAME - The present invention relates to a method for fabricating a FinFET on a substrate. The method comprises providing a substrate with an active semiconductor layer on an insulator layer, and concurrently fabricating trench isolation regions in the active semiconductor layer for electrically isolating different active regions in the active semiconductor layer from each other, and trench gate-isolation regions in the active semiconductor layer for electrically isolating at least one gate region of the FinFET in the active semiconductor layer from a fin-shaped channel region of the FinFET in the active semiconductor layer. | 01-13-2011 |
| 20110079848 | SEMICONDUCTOR DEVICE WITH DUMMY GATE ELECTRODE AND CORRESPONDING INTEGRATED CIRCUIT AND MANUFACTURING METHOD - A field effect transistor semiconductor device configuration is described, which is particularly suitable for use in DC: DC converters associated with logic circuitry. The device includes a first gate electrode ( | 04-07-2011 |
| 20110084356 | LOCAL BURIED LAYER FORMING METHOD AND SEMICONDUCTOR DEVICE HAVING SUCH A LAYER - The present invention discloses a method of forming a local buried layer ( | 04-14-2011 |
| 20110089498 | INTEGRATION OF LOW AND HIGH VOLTAGE CMOS DEVICES - A method of fabricating a semiconductor device is provided that includes providing a semiconductor substrate having a first portion and a second portion, forming a first transistor in the first portion of the substrate, the first transistor being operable at a first voltage, and forming a second transistor in the second portion of the substrate, the second transistor being operable at a second voltage greater than the first voltage. The formation of the second transistor includes forming an extended feature of the second transistor with a photomask that is used to adjust a threshold voltage of the first transistor. | 04-21-2011 |
| 20110101452 | TRENCH GATE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF - A trench-gate semiconductor device configuration is provided which is suitable for incorporation in integrated circuits, together with methods for its manufacture. A self-aligned drain region ( | 05-05-2011 |
