| Patent application number | Description | Published |
|---|
| 20080239833 | Readout of multi-level storage cells - A multi-level sensing scheme compares the state of a multi-level storage cell with monotonously changing reference states, which are associated to different information values. That particular information value is identified to be the information stored in the multi-level storage cell, which has associated that reference state which, in a changing direction, firstly exceeds the state. | 10-02-2008 |
| 20080298121 | METHOD OF OPERATING PHASE-CHANGE MEMORY - A method of operating a phase-change memory array. The method may comprise causing a first current to flow through a phase-change memory element in a first direction and causing a second current to flow through the memory element in a second direction. | 12-04-2008 |
| 20090034343 | DATA RETENTION MONITOR - A data retention monitor for a memory cell including a voltage source and a voltage comparator. The voltage source is adapted to provide a selectable voltage to the memory cell. The selectable voltage includes a read voltage and a test voltage, with the test voltage being greater than the read voltage. The voltage comparator is adapted to compare a voltage of the memory cell with a reference voltage after the provision of the selectable voltage to the memory cell. The memory cell retains data when the memory cell voltage generated at least in part by the test voltage is substantially equal to the reference voltage. | 02-05-2009 |
| 20100065891 | Compact Memory Arrays - Embodiments of the invention describe compact memory arrays. In one embodiment, the memory cell array includes first, second, and third gate lines disposed over a substrate, the second gate lines are disposed between the first and the third gate lines. The first, the second, and the third gate lines form adjacent gate lines of the memory cell array. The memory cell array further includes first metal lines disposed over the first gate lines, the first metal lines coupled to the first gate lines; second metal lines disposed over the second gate lines, the second metal lines coupled to the second gate lines; and third metal lines disposed over the third gate lines, the third metal lines coupled to the third gate lines. The first metal lines, the second metal lines and the third metal lines are disposed in different metallization levels. | 03-18-2010 |
| 20100103722 | METHOD OF PROGRAMMING RESISTIVITY CHANGING MEMORY - A method of operating an integrated circuit includes determining a resistance value of at least one resistivity-changing memory cell when the memory cell is in a low-resistance state, the at least one resistivity-changing memory cell configured to be programmable to at least the low-resistance state and a high-resistance state, comparing the resistance value to a threshold value, selecting, based on the comparison, a cell reset process to be employed for programming the at least one resistivity-changing memory cell to the high-resistance state. The selecting includes selecting a predetermined reset process as the cell reset process when the resistance value is less than the threshold value, and adjusting the predetermined process and selecting the adjusted predetermined reset process as the cell reset process when the resistance value is at least equal to the threshold value. | 04-29-2010 |
| 20100146189 | Programming Non Volatile Memories - Non volatile memories and methods of programming thereof are disclosed. In one embodiment, the method of programming a memory array includes receiving a series of data blocks, each data block having a number of bits that are to be programmed, determining the number of bits that are to be programmed in a first data block, determining the number of bits that are to be programmed in a second data block, and writing the first and the second data blocks into a memory array in parallel if the sum of the number of bits that are to be programmed in the first data block and the second data block is not greater than a maximum value. | 06-10-2010 |
| 20100199148 | System and Method for Constructing Multi-Write Error Correcting Code - An embodiment of the invention relates to a memory device and a related method. In an embodiment, a check matrix for an error-correcting code is formed so that sets of input data bits can be written, wherein each set of input data bits generates one set of error-correcting code bits that can be written independently of each other and in an arbitrary order. An error-correcting code is thereby produced without the need to erase or copy any existing, originally written bit upon presentation of new input data. | 08-05-2010 |
| 20100202218 | System and Method for Level Shifter - In one embodiment, a bit-line interface is disclosed. The bit-line interface has a multiplexer having a plurality of bit-line outputs, and a write path coupled to a multiplexer signal input. The bit-line interface also has a read path coupled to the multiplexer signal input, wherein the read path and the write path share at least one component. | 08-12-2010 |
| 20100226178 | APPARATUS AND METHODS FOR CORRECTING OVER-ERASED FLASH MEMORY CELLS - A method and flash memory device that correct over-erased memory cells are described. The device includes flash memory cells, erase circuitry, measuring circuitry, and a pulse generator. The method includes performing an erase operation on a first plurality of memory cells, measuring at least one memory cell of a second plurality of memory cells, and if an over-erased memory cell is detected in measuring the second plurality of cells, applying one or more programming pulses to the one or more over-erased cells, the one or more programming pulses cumulatively sufficient to correct a cell in a maximum over-erased state. Also described is a method that registers over-erased cells for programming and applies one or more programming pulses to the registered over-erased cells, the one or more programming pulses cumulatively sufficient to correct a cell in a maximum over-erased state. | 09-09-2010 |
| 20110103150 | NON-VOLATILE MEMORY WITH PREDICTIVE PROGRAMMING - A method of operating an integrated circuit includes applying at least one first programming pulse to a plurality of non-volatile memory cells to adjust a level of a storage parameter of each of the non-volatile memory cells, the at least one first programming pulse defined by a plurality of pulse parameters each having a fixed valued, and determining a fail count by measuring the number of non-volatile memory cells of the plurality of non-volatile memory cells having a storage parameter level exceeding a verify level. The method further includes determining a change in an programming behavior of the plurality of non-volatile memory cells based on the fail count, adjusting a value of at least one pulse parameter of at least one second programming pulse defined by the plurality of pulse parameters to a desired value based on the change in programming behavior, and applying the at least one second programming pulse to the plurality non-volatile memory cells. | 05-05-2011 |
