| Patent application number | Description | Published |
|---|
| 20090003046 | MEMORY WITH DYNAMIC REDUNDANCY CONFIGURATION - One embodiment of the invention relates to a method for repairing a memory array. In the method, a group of at least one memory cell is dynamically analyzed to determine whether the memory array includes at least one faulty cell that no longer properly stores data. If the group includes at least one faulty cell, at least the at least one faulty cell is associated with at least another cell. Other methods, devices, and systems are also disclosed. | 01-01-2009 |
| 20090045385 | INTEGRATED CIRCUIT INCLUDING MEMORY ELEMENT WITH HIGH SPEED LOW CURRENT PHASE CHANGE MATERIAL - An integrated circuit includes a first electrode, a second electrode, and a memory element coupled to the first electrode and to the second electrode, the memory element includes fast-operation resistance changing material doped with dielectric material. | 02-19-2009 |
| 20090046498 | INTEGRATED CIRCUIT INCLUDING MEMORY HAVING REDUCED CROSS TALK - An integrated circuit includes a first electrode, a second, a first resistivity changing material contacting the first electrode at a first interface, and a second resistivity changing material contacting the second electrode at a second interface. A direct communication path between the first interface and the second interface is greater than the lateral distance. | 02-19-2009 |
| 20090046499 | INTEGRATED CIRCUIT INCLUDING MEMORY HAVING LIMITED READ - An integrated circuit including a memory with an array of memory cells, each memory cell comprising a non-volatile memory element; and a limited read circuit communicatively coupled to the array of memory cells. | 02-19-2009 |
| 20090147563 | INTEGRATED CIRCUIT FOR PROGRAMMING A MEMORY ELEMENT - An integrated circuit includes a resistance changing memory element and a circuit. The circuit is configured to program the memory element by iteratively applying a variable program pulse to the memory element until a resistance of the memory element crosses a first reference resistance. The variable program pulse is adjusted for each iteration such that the resistance of the memory element approaches the first reference resistance. | 06-11-2009 |
| 20090154226 | INTEGRATED CIRCUIT INCLUDING QUENCH DEVICES - An integrated circuit includes a line, at least two quench devices coupled to the line, and a resistivity changing material memory cell coupled to the line. The at least two quench devices are configured to quench a write signal on the line during a write operation of the memory cell. | 06-18-2009 |
| 20090154227 | INTEGRATED CIRCUIT INCLUDING DIODE MEMORY CELLS - The integrated circuit includes a transistor and a contact coupled to the transistor. The integrated circuit includes a first diode resistivity changing material memory cell coupled to the contact and a second diode resistivity changing material memory cell coupled to the contact. The second diode resistivity changing material memory cell is positioned above the first diode resistivity changing material memory cell. | 06-18-2009 |
| 20090161415 | INTEGRATED CIRCUIT FOR SETTING A MEMORY CELL BASED ON A RESET CURRENT DISTRIBUTION - An integrated circuit includes an array of resistance changing memory cells and a first circuit. The first circuit is configured to set a selected memory cell to a crystalline state by applying a decreasing stair step pulse to the selected memory cell. The pulse is based on a reset current distribution for the array of memory cells. | 06-25-2009 |
| 20090196093 | STACKED DIE MEMORY - A memory includes a first die including a first array of phase change memory cells and a second die including a second array of phase change memory cells. The second die is stacked above the first die. The memory includes lines configured to access the first die and the second die. The first die and the second die are enclosed in a single package. | 08-06-2009 |
| 20090237983 | INTEGRATED CIRCUIT INCLUDING MEMORY ELEMENT DOPED WITH DIELECTRIC MATERIAL - An integrated circuit includes a first electrode, a second electrode, and a damascene structured memory element coupled to the first electrode and the second electrode. The memory element has a height and a width. The height is greater than or equal to the width. The memory element includes resistance changing material doped with dielectric material. | 09-24-2009 |
| 20090285014 | INTEGRATED CIRCUIT AND METHOD FOR SWITCHING A RESISTIVELY SWITCHING MEMORY CELL - An integrated circuit and method for switching a resistively switching memory cell. One embodiment provides an initial pulse and at least one escalated pulse in case the memory cell did not switch. | 11-19-2009 |
| 20090310401 | INTEGRATED CIRCUIT INCLUDING A MEMORY ELEMENT PROGRAMMED USING A SEED PULSE - An integrated circuit includes a resistance changing memory element and a circuit. The circuit is configured to program the memory element to a crystalline state from an amorphous state by applying a seed pulse to the memory element followed by a set pulse. | 12-17-2009 |
| 20100002498 | INTEGRATED CIRCUIT FOR PROGRAMMING A MEMORY CELL - An integrated circuit includes an array of resistance changing memory cells. The array includes a first portion. The integrated circuit includes a circuit configured to apply a set pulse having a first pulse width to a first memory cell in the first portion to set the first memory cell. The first pulse width is based on a predetermined error percentage for the first portion. | 01-07-2010 |
| 20100044669 | INTEGRATED CIRCUIT INCLUDING MEMORY CELL HAVING CUP-SHAPED ELECTRODE INTERFACE - An integrated circuit includes a first electrode and a cup-shaped electrode interface coupled to the first electrode. The integrated circuit includes a dielectric spacer at least partially laterally enclosed by the electrode interface and a resistance changing material laterally enclosed by the spacer and contacting the electrode interface. The integrated circuit includes a second electrode coupled to the resistance changing material. | 02-25-2010 |
| 20100290277 | RESISTIVE MEMORY CELL ACCESSED USING TWO BIT LINES - An integrated circuit includes a first bit line and a resistance changing memory element coupled to the first bit line. The integrated circuit includes a second bit line and a heater coupled to the second bit line. The integrated circuit includes an access device coupled to the resistance changing memory element and the heater. | 11-18-2010 |
