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Jammy
Raj Jammy, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20100081278 | Methods for Nanoscale Feature Imprint Molding - Methods for fabricating nanoscale features are disclosed. One technique involves depositing onto a substrate, where the first layer may be a silicon layer and may subsequently be etched. A second layer and third layer may be deposited on the etch first layer, followed by the deposition of a silicon cap. The second and third layer may be etched, exposing edges of the second and third layers. The cap and first layer may be removed and either the second or third layer may be etched, creating a nanoscale pattern. | 04-01-2010 |
Rajarao Jammy, Austin, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20090127121 | METHOD AND APPARATUS FOR ELECTROPLATING ON SOI AND BULK SEMICONDUCTOR WAFERS - An electroplating apparatus and method for depositing a metallic layer on the surface of a wafer is provided wherein said apparatus and method do not require physical attachment of an electrode to the wafer. The surface of the wafer to be plated is positioned to face the anode and a plating fluid is provided between the wafer and the electrodes to create localized metallic plating. The wafer may be positioned to physically separate and lie between the anode and cathode so that one side of the wafer facing the anode contains a catholyte solution and the other side of the wafer facing the cathode contains an anolyte solution. Alternatively, the anode and cathode may exist on the same side of the wafer in the same plating fluid. In one example, the anode and cathode are separated by a semi permeable membrane. | 05-21-2009 |
Rajarao Jammy, Hopewell Junction NY
| Patent application number | Description | Published |
|---|---|---|
| 20090011610 | SELECTIVE IMPLEMENTATION OF BARRIER LAYERS TO ACHIEVE TRESHOLD VOLTAGE CONTROL IN CMOS DEVICE FABRICATION WITH HIGH K DIELECTRICS - A method of forming a CMOS structure, and the device produced therefrom, having improved threshold voltage and flatband voltage stability. The inventive method includes the steps of providing a semiconductor substrate having an nFET region and a pFET region; forming a dielectric stack atop the semiconductor substrate comprising an insulating interlayer atop a high k dielectric; removing the insulating interlayer from the nFET region without removing the insulating interlayer from the pFET region; and providing at least one gate stack in the pFET region and at least one gate stack in the nFET region. The insulating interlayer can be AlN or AlO | 01-08-2009 |