| Patent application number | Description | Published |
|---|
| 20090125786 | Mechanism for Adjacent-Symbol Error Correction and Detection - According to one embodiment a computer system is disclosed. The computer system includes memory. The memory includes two or more rows, where each row has a plurality of memory devices. The computer system also includes a chipset. The chipset includes a detection/correction circuit to detect single and double symbol errors and correct single symbol errors for each memory row, and markers to maintain a log of errors within each memory row. | 05-14-2009 |
| 20090171875 | SYSTEMS, METHODS AND APPARATUSES FOR RANK COORDINATION - Embodiments of the invention are generally directed to systems, methods, and apparatuses for rank coordination. In some embodiments, a host includes rank coordination logic. The rank coordination logic may include performance measurement logic to measure a performance of a memory channel and dwell period control logic to select a length of a dwell period based, at least in part, on the performance of the memory channel. Other embodiments are described and claimed. | 07-02-2009 |
| 20090172440 | COUPLED LOW POWER STATE ENTRY AND EXIT FOR LINKS AND MEMORY - In some embodiments if a new request appears in a receive queue relating to a resource, and a controlled direction of the resource is in a low power state, a method starts an exit of the controlled direction after a delay. If receive direction of power control of the resource is in a low power state and preparation is being made to enter a low power state at the controlled direction, then the method decreases a watch and wait period that occurs prior to moving into the low power state at the controlled direction. Other embodiments are described and claimed. | 07-02-2009 |
| 20090172441 | HARDWARE PROACTIVE IMPLEMENTATION FOR ACTIVE MODE POWER CONTROL OF PLATFORM RESOURCES - In some embodiments, estimating a duration of an idle period gap of a lower power state of a resource by exponentially smoothing successive idle period gaps. Other embodiments are described and claimed. | 07-02-2009 |
| 20090172442 | SYSTEM AND METHOD FOR MEMORY PHASE SHEDDING - Embodiments of the invention supply power to DRAM or other memory devices with a multi-phase voltage regulator. A power controller coupled to the multi-phase voltage regulator causes one or more phases of the multi-phase voltage regulator to be activated or deactivated (shed) according to predetermined criteria. Embodiments of the invention thus improve power management by providing one or more reduced power states for the memory devices. Other embodiments are described. | 07-02-2009 |
| 20090172681 | SYSTEMS, METHODS AND APPARATUSES FOR CLOCK ENABLE (CKE) COORDINATION - Embodiments of the invention are generally directed to systems, methods, and apparatuses for clock enable (CKE) coordination. In some embodiments, a memory controller includes logic to predict whether a scheduled request will be issued to a rank. The memory controller may also include logic to predict whether a scheduled request will not be issued to the rank. In some embodiments, the clock enable (CKE) is asserted or de-asserted to a rank based, at least in part, on the predictions. Other embodiments are described and claimed. | 07-02-2009 |
| 20090249097 | OPTIMIZING PERFORMANCE AND POWER CONSUMPTION DURING MEMORY POWER DOWN STATE - Methods and apparatus relating to optimization of performance and/or power consumption during memory power down state are described. In an embodiment, a memory controller may include logic to cause one or more ranks of a DIMM to enter a clock enable slow mode. Other embodiments are also described. | 10-01-2009 |
| 20100169729 | ENABLING AN INTEGRATED MEMORY CONTROLLER TO TRANSPARENTLY WORK WITH DEFECTIVE MEMORY DEVICES - Embodiments of the invention are generally directed to systems, methods, and apparatuses for enabling an integrated memory controller to transparently work with defective memory devices. In some embodiments, a marginal condition is imposed on a memory module during normal operations of the memory module. The term “marginal condition” refers to a condition that is out of compliance with a specified (or “normal”) operating condition for the memory module. The memory module may exhibit failures in response to the marginal conditions and compensating mechanisms may mitigate the failures. | 07-01-2010 |
