Patent application number | Description | Published |
20080235501 | Method For Detecting and Correcting Firmware Corruption - A method for detecting and correcting firmware corruption in a system having a host communicatively coupled to an electronic apparatus, the electronic apparatus having a hardware unit communicatively coupled to a non-volatile memory, includes determining via the hardware unit whether firmware on the non-volatile memory is corrupted; if the firmware is determined to be corrupted, then: invoking a communication driver resident in the hardware unit to establish bi-directional communications between the host and the electronic apparatus; and initiating a firmware download from the host to update the firmware on the non-volatile memory to an uncorrupted state. | 09-25-2008 |
20080239338 | Method For Performing Error Diffusion Halftoning of an Image - A method for performing error diffusion halftoning of an image includes subdividing the image into a plurality of tiles, the plurality of tiles including a first tile and a second tile adjacent to the first tile; performing error diffusion processing of the first tile; and performing the error diffusion processing of the second tile based on an output phase of the first tile. | 10-02-2008 |
20090089346 | Method For Performing A Division Operation In A System - A method for performing a division operation in a system includes a) determining an approximate quotient of a numerator value and a denominator value; b) determining an initial error of the approximate quotient; c) determining a quotient adjustment value based on the initial error; d) determining whether to apply the quotient adjustment value to the approximate quotient; e) if the determination at d) is YES, then applying the quotient adjustment value to the approximate quotient; f) determining an iterative error of the approximate quotient; g) updating the quotient adjustment value based on the iterative error; h) repeating acts d) through g) until the determination at d) is NO, thereby determining a final value for the approximate quotient; i) generating an integer quotient based on the final value of the approximate quotient; and j) using the integer quotient with regard to at least one aspect of the system. | 04-02-2009 |
20090091808 | Method for Dynamically Compensating for a Faulty Pixel in a Scan Line Generated by a Scanner - A method for dynamically compensating for a faulty pixel in a scan line of a scanner having an image sensor with a plurality of sensor pixels includes generating digitized scan data; processing the digitized scan data to compensate for any faulty pixels of the plurality of sensor pixels to form compensated scan data; processing the compensated scan data to apply offset and gain correction to the compensated scan data to form calibrated scan data; processing the calibrated scan data to adjust the calibrated scan data to compensate for human visual perception to form final scan data; and storing the final scan data in a scanner image memory. | 04-09-2009 |
20100091333 | Method and Printer System for Reducing Image Print Grain Effect - A method and an imaging apparatus for reducing print grain effect in an image to be printed by a printing device are disclosed. One or more flat field areas, each comprising at least one flat field pixel, are detected in the image. A color value of each detected flat field pixel in the one or more flat field areas is modified using a unique flat field optimized color lookup table. The modification of the color value of each flat field pixel in the image reduces the print grain effect in the image to be printed by the printing device. | 04-15-2010 |
20100245430 | Method for Minimizing Printing Defects due to Missing Nozzle in Media Processing Device - Disclosed is a method for printing a media sheet in a media processing device. The method includes aligning a first portion of a printhead of the media processing device to a print area of the media sheet. The method further includes printing the print area of the media sheet by traversing the printhead over the print area in a first direction. The printing is performed by the first portion. Further, the method includes aligning a second portion of the printhead to the print area by adjusting the media sheet relative to the printhead by an index distance in a direction perpendicular to the first direction. Thereafter, the method includes reprinting the print area by traversing the printhead over the print area in a second direction opposite to the first direction. The reprinting is performed by the second portion. | 09-30-2010 |
20100309489 | MEDIA PROCESSING DEVICE AND METHOD OF PRINTING OF RASTER DATA - A method for printing of raster data in a media processing device is disclosed. The method includes identifying an attribute of a set of raster lines of the raster data. The method further includes determining at least one print mode from a plurality of print modes based on the attribute. Each print mode of the plurality of print modes is configured to print the set of raster lines of the raster data. Furthermore, the method includes printing the set of raster lines of the raster data in the at least one print mode. | 12-09-2010 |
20110047423 | Integrated Circuit Including a Programmable Logic Analyzer with Enhanced Analyzing and Debugging Capabilities and a Method Therefor - An integrated circuit including a logic analyzer with enhanced analyzing and debugging capabilities and a method therefor. In one embodiment of the present invention, an embedded logic analyzer (ELA) receives a plurality of signals from a plurality of buses within an integrated circuit (IC). The ELA includes an interconnect module to select a trigger signal and/or a sampled signal from the plurality of received signals. A trigger module sets at least one trigger condition and detects if the trigger signal satisfies the at least one trigger condition. When the trigger condition is satisfied, an output module performs at least one task based upon the satisfied at least one trigger condition. If a sampling process is initiated by the output module, the plurality of sampled signals is sampled and may be stored in a memory. The capability of the output module to perform multiple user-defined tasks enhances the debugging capability of the ELA and makes it more versatile. | 02-24-2011 |
20110047424 | INTEGRATED CIRCUIT INCLUDING A PROGRAMMABLE LOGIC ANALYZER WITH ENHANCED ANALYZING AND DEBUGGING CAPABILITES AND A METHOD THEREFOR - An integrated circuit including a logic analyzer with enhanced analyzing and debugging capabilities and a method therefor. In one embodiment of the present invention, an embedded logic analyzer (ELA) receives a plurality of signals from a plurality of buses within an integrated circuit (IC). The ELA includes an interconnect module to select a trigger signal and/or a sampled signal from the plurality of received signals. A trigger module sets at least one trigger condition and detects if the trigger signal satisfies the at least one trigger condition. When the trigger condition is satisfied, an output module performs at least one task based upon the satisfied at least one trigger condition. If a sampling process is initiated by the output module, the plurality of sampled signals is sampled and may be stored in a memory. The capability of the output module to perform multiple user-defined tasks enhances the debugging capability of the ELA and makes it more versatile. | 02-24-2011 |
20110047427 | Integrated Circuit Including a Programmable Logic Analyzer with Enhanced Analyzing and Debugging Capabilities and a Method Therefor - An integrated circuit including a logic analyzer with enhanced analyzing and debugging capabilities and a method therefor. In one embodiment, an integrated circuit includes a logic analyzer having a first input receiving a plurality of signals and an output for providing an indication of a detection, by the logic analyzer, of at least one trigger event; and a built in self test block having a first input for receiving one or more of the signals appearing at the first input of the logic analyzer, a second input coupled to the output of the logic analyzer for selectively enabling the BIST block, the BIST block generating and maintaining a signature based upon the first and second inputs thereof. | 02-24-2011 |
20110167311 | System and Method for Analyzing an Electronics Device Including a Logic Analyzer - A system for testing or debugging a system including the integrated circuit having an embedded logic analyzer. In one embodiment, the system includes a computing device coupled to the logic analyzer for receiving the at least one output. A user interface run on the computing device assigns an attribute to at least one signal associated with the logic analyzer, determines a new signal or value not provided by the logic analyzer, the new signal or value being based upon the at least one signal as received from the logic analyzer and upon a predetermined definition, and presents the new signal or value to a system user. | 07-07-2011 |
20120144256 | System and Method for Analyzing an Electronics Device Including a Logic Analyzer - A system for testing or debugging a device under test having an embedded logic analyzer. In one embodiment, the system includes software stored in non-transitory memory for testing a device under test having an embedded logic analyzer, the software program product having instructions which, when executed by a computing device associated with the device under test cause the computing device to reconstruct signals of interest in the device under test based at least in part upon signals captured by the embedded logic analyzer during the test or debug session, and cause the computing device to display the reconstructed signals of interest to a user of the computing device. | 06-07-2012 |