| Patent application number | Description | Published |
|---|
| 20090089566 | SUPPORTING ADVANCED RAS FEATURES IN A SECURED COMPUTING SYSTEM - Systems and methods for enabling Reliability, Availability & Serviceability features after launching a secure environment under the control of LaGrande Technology (LT), or comparable security technology, without compromising security are provided. In one embodiment, the method comprises adding at least one specific capability to a processor to enable at least one of CPU hot-plug, CPU migration, CPU hot removal and capacity on demand. | 04-02-2009 |
| 20110153924 | CORE SNOOP HANDLING DURING PERFORMANCE STATE AND POWER STATE TRANSITIONS IN A DISTRIBUTED CACHING AGENT - A method and apparatus may provide for detecting a performance state transition in a processor core and bouncing a core snoop message on a shared interconnect ring in response to detecting the performance state transition. The core snoop message may be associated with the processor core, wherein a plurality of processor cores may be coupled to the shared interconnect ring via a distributed last level cache controller. | 06-23-2011 |
| 20110153948 | SYSTEMS, METHODS, AND APPARATUS FOR MONITORING SYNCHRONIZATION IN A DISTRIBUTED CACHE - Systems, apparatus, and method of monitoring synchronization in a distributed cache are described. In an exemplary embodiment, a first and second processing core process a first and second thread respectively. A first and second distributed cache slices store data for either or both of the first and second processing cores. A first and second core interface co-located with the first and second processing cores respectively maintain a finite state machine (FSM) to be executed in response to receiving a request from a thread of its co-located processing core to monitor a cache line in the distributed cache. | 06-23-2011 |
| 20110161585 | PROCESSING NON-OWNERSHIP LOAD REQUESTS HITTING MODIFIED LINE IN CACHE OF A DIFFERENT PROCESSOR - Methods and apparatus to efficiently process non-ownership load requests hitting modified line (M-line) in cache of a different processor are described. In one embodiment, a first agent changes the state of a first data and forwards it to a second, requesting agent who stores the first data in an alternative modified state. Other embodiments are also described. | 06-30-2011 |
| 20110161601 | INTER-QUEUE ANTI-STARVATION MECHANISM WITH DYNAMIC DEADLOCK AVOIDANCE IN A RETRY BASED PIPELINE - Methods and apparatus relating to an inter-queue anti-starvation mechanism with dynamic deadlock avoidance in a retry based pipeline are described. In one embodiment, logic may arbitrate between two queues based on various rules. The queues may store data including local or remote requests, data responses, non-data responses, external interrupts, etc. Other embodiments are also disclosed. | 06-30-2011 |
| 20110161705 | MULTIPLE-QUEUE MULTIPLE-RESOURCE ENTRY SLEEP AND WAKEUP FOR POWER SAVINGS AND BANDWIDTH CONSERVATION IN A RETRY BASED PIPELINE - Methods and apparatus relating to multiple-queue multiple-resource entry sleep and wakeup for power savings and bandwidth conservation in a retry based pipeline are described. In one embodiment, a bit indicates whether a corresponding queue entry is asleep or awake with respect to arbitration for resources in a retry based pipeline. Furthermore, multiple entries from different queues may be grouped together and multiple resources may be grouped together. Other embodiments are also disclosed. | 06-30-2011 |
| 20110161769 | RETRY BASED PROTOCOL WITH SOURCE/RECEIVER FIFO RECOVERY AND ANTI-STARVATION MECHANISM TO SUPPORT DYNAMIC PIPELINE LENGTHENING FOR ECC ERROR CORRECTION - Methods and apparatus relating to retry based protocol with source/receiver FIFO (First-In, First-Out) buffer recovery and anti-starvation mechanism to support dynamic pipeline lengthening for ECC error correction are described. In an embodiment, upon detection of an error, a portion of transmitted data is stored in one or more storage devices before retransmission. Other embodiments are also described and claimed. | 06-30-2011 |
| 20110191542 | SYSTEM-WIDE QUIESCENCE AND PER-THREAD TRANSACTION FENCE IN A DISTRIBUTED CACHING AGENT - Methods and apparatus relating to system-wide quiescence and per-thread transaction fence in a distributed caching agent are described. Some embodiments utilize messages, counters, and/or state machines that support system-wide quiescence and per-thread transaction fence flows. Other embodiments are also disclosed. | 08-04-2011 |
