| Patent application number | Description | Published |
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| 20100073073 | MICROPROCESSOR WITH SUBSTRATE BIAS CLAMPS - A microprocessor including a substrate bias rail providing a bias voltage during a first operating mode, a supply node providing a core voltage, a clamp device coupled between the bias rail and the supply node, and control logic. The control logic turns on the clamp device to clamp the bias rail to the supply node during a second operating mode and turns off the clamp device during the first operating mode. The clamp devices may be implemented with P-channel and N-channel devices. Level shift and buffer circuits may be provided to control the clamp devices based on substrate bias voltage levels. The microprocessor may include a substrate with first and second areas each including separate substrate bias rails. The control logic separately turns on and off clamp devices to selectively clamp the substrate bias rails in the first and second areas based on various power modes. | 03-25-2010 |
| 20100073074 | MICROPROCESSOR WITH SELECTIVE SUBSTRATE BIASING FOR CLOCK-GATED FUNCTIONAL BLOCKS - A microprocessor according to one embodiment includes a supply node providing a core voltage, a functional block, a charge node, select logic, and substrate bias logic. The functional block has multiple power modes and includes one or more semiconductor devices and a substrate bias rail routed within the functional block and coupled to a substrate connection of at least one semiconductor device. The select logic couples the substrate bias rail to the charge node when the functional block is in a low power mode and clamps the substrate bias rail to the supply node when the functional block is in a full power mode. The substrate bias logic charges the charge node to a bias voltage at an offset voltage relative to the core voltage when the functional block is in the low power mode. Semiconductor devices may be provided to clamp or otherwise couple the bias rail. | 03-25-2010 |
| 20100085108 | SYSTEM AND METHOD FOR ADJUSTING SUPPLY VOLTAGE LEVELS TO REDUCE SUB-THRESHOLD LEAKAGE - A voltage regulation module which includes an adjustable voltage which reduces the positive supply voltage and increases the negative supply voltage during a lower power mode. The voltage regulation module includes a voltage generator which provides an N-type substrate bias voltage at the normal operating voltage level of the positive supply voltage and which provides a P-type substrate bias voltage at the normal operating voltage level of the negative supply voltage during the lower power mode. Thus, the supply voltage levels are adjusted rather than the substrate bias voltages during the lower power mode. The voltage generator may be implemented as a voltage regulator, or may be implemented as a bias generator or charge pump or the like. | 04-08-2010 |
| 20100262729 | CONFIGURABLE BUS TERMINATION FOR MULTI-CORE/MULTI-PACKAGE PROCESSOR CONFIGURATIONS - A multi-core/multi-package bus termination apparatus includes a configuration array and a plurality of drivers. The configuration array generates location/protocol signals that each direct one of the plurality of drivers on the bus to employ location-based bus termination or protocol-based bus termination. The plurality of drivers is coupled to the plurality of location/protocol signals, a plurality of location signals, a bus ownership signal, and a multi-package signal. Each of the plurality of drivers controls how one of a plurality of nodes is driven responsive to a first state of one of the plurality of location/protocol signals. Each has configurable multi-core/multi-package logic controls pull-up logic, first pull-down logic, and second pull-down logic according to location-based termination rules if the first state indicates the location-based termination, and controls the pull-up logic, the first pull-down logic, and the second pull-down logic according to protocol-based termination rules if the first state indicates the protocol-based termination. | 10-14-2010 |
| 20100262733 | PROTOCOL-BASED BUS TERMINATION FOR MULTI-CORE PROCESSORS - A multi-core bus termination apparatus includes a protocol analyzer and a plurality of drivers. The protocol analyzer is disposed within a processor core and configured to receive one or more protocol signals, and is configured to indicate whether or not the processor core owns the bus. The plurality of drivers is coupled to the protocol analyzer. Each of the plurality of drivers has one of a corresponding plurality of nodes, and each is configured to control how the one of the corresponding plurality of nodes is driven responsive whether or not the processor core owns the bus. Each of the plurality of drivers has protocol-based multi-core logic. The protocol-based multi-core logic is configured to enable pull-up logic if the processor core owns the bus, and is configured to disable the pull-up logic if the processor core does not own the bus. | 10-14-2010 |
| 20100262747 | LOCATION-BASED BUS TERMINATION FOR MULTI-CORE PROCESSORS - A multi-core bus termination apparatus includes a location array and a plurality of drivers. The location array generates a plurality of location signals that indicate locations on the bus of a corresponding plurality of nodes that are coupled to the bus, where the locations comprise either an internal location or a bus end location. Each of the plurality of drivers has one of the corresponding plurality of nodes, and controls how the one of the corresponding plurality of nodes is driven responsive to a state of a corresponding one of the plurality of location signals. Each of the plurality of drivers has configurable multi-core logic. The configurable multi-core logic enables pull-up logic and first pull-down logic if the state indicates the bus end location. The configurable multi-core logic disables the pull-up logic and to enable the first pull-down logic and second pull-down logic if the state indicates the internal location. | 10-14-2010 |
| 20110037508 | REGISTERS WITH REDUCED VOLTAGE CLOCKS - A register circuit including a level shift circuit, a latch isolation circuit, and a keeper circuit for registering data with a lower voltage clock signal. The level shift circuit switches a level shift node between a reference voltage level and an upper voltage level in response to a clock node and an input node. The clock node toggles between the reference voltage level and a lower voltage level. The latch isolation circuit isolates an output node from the input node when the clock node is at the reference voltage level, and asserts the output node to one of the reference voltage level and an upper voltage level based on a state of the input node when the clock node is at the lower voltage level. The keeper circuit maintains a state of the output node when the clock node is at the reference voltage level. | 02-17-2011 |
| 20110058641 | FAST DYNAMIC REGISTER - A fast dynamic register circuit including first and second precharge circuits, a keeper circuit and an output circuit. The first and second precharge circuits each precharge a corresponding one of a pair of precharge nodes and cooperate to minimize setup and hold times. If an input data node is low when the clock goes high, the first precharge node remains high causing the second precharge node to be discharged. Otherwise if the input node is high, the first precharge node is discharged and the second remains charged. Once either precharge node is discharged, the output state of the register remains fixed until the next rising clock edge independent of changes of the input data node. The fast dynamic register may be implemented with multiple inputs to perform common logic operations, such as OR, NOR, AND and NAND logic operations. | 03-10-2011 |
