# James A. Bailey, Snowflake US

## James A. Bailey, Snowflake, AZ US

Patent application number | Description | Published |
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20090128389 | Multi-bit Per Stage Pipelined Analog to Digital Converters - Various embodiments of the present invention provide systems and circuits that provide for conversion of analog signals to digital signals. For example, various embodiments of the present invention provide pipelined analog to digital converters. Such converters include a sub-converter and a residue amplifier. The sub-converter receives an analog input, and provides a digital representation of the analog input including a number of bits. A gain of the residue amplifier is controlled by selectably setting a group of switches. Each of the number of bits output from the sub-converter electrically controls a respective one of the switches. | 05-21-2009 |

20090128391 | SYSTEMS AND METHODS FOR PIPELINED ANALOG TO DIGITAL CONVERSION - Various embodiments of the present invention provide systems and circuits that provide for conversion of analog signals to digital signals. For example, various embodiments of the present invention provide methods for performing analog to digital conversions that include providing an analog to digital converter with a residue amplifier that is associated with a first capacitance set that includes a first feedback capacitor and first set of input capacitors, and a second capacitance set that includes a second feedback capacitor and second set of input capacitors. The methods further include performing a first sample of an analog input voltage by charging the first set of input capacitors from the analog voltage input during a first period; amplifying the first sample during a second period; performing a second sample of the analog input voltage by charging the second set of input capacitors from the analog voltage input during a third period; and amplifying the second sample during a fourth period. | 05-21-2009 |

20090195422 | AREA AND POWER EFFICIENT ANALOG TO DIGITAL CONVERTER AND METHODS FOR USING SUCH - Various embodiments of the present invention provide systems and circuits that provide for conversion of analog signals to digital signals. For example, various embodiments of the present invention provide analog to digital converter circuits that are capable of converting an input voltage to a digital representation thereof. Such analog to digital converter circuits include at least a first comparator and a second comparator. An input of the first comparator is electrically coupled to a first storage device, and another input of the first comparator is electrically coupled to the input voltage. An input of the second comparator is electrically coupled to a second storage device, and another input of the second comparator is electrically coupled to the input voltage. The analog to digital converter circuits further include a reference voltage generation circuit that provides the first reference voltage to the first storage device, and subsequently provides the second reference voltage to the second storage device. | 08-06-2009 |

20090195432 | Systems and Methods for Analog to Digital Conversion - Various embodiments of the present invention provide systems and circuits that provide for conversion of analog signals to digital signals. For example, various embodiments of the present invention provide partially clocked, multi-step analog to digital converters. Such analog to digital converters include a clocked fine conversion stage, a clocked coarse conversion stage, and a clock circuit. The fine conversion stage includes a first group of comparators clocked by a first clock and a second group of comparators clocked by a second clock. The first group of comparators is operable to compare an input voltage with a first fine reference voltage range, and the second group of comparators is operable to compare the input voltage with a second fine reference voltage range. The coarse conversion stage includes a group of clocked comparators that are operable to compare the input voltage with a coarse reference voltage range. The clock circuit selectably asserts one of the first clock and the second clock based at least in part on an output of the second conversion stage. | 08-06-2009 |

20110018748 | Systems and Methods for Two Tier Sampling Correction in a Data Processing Circuit - Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is disclosed that includes an analog to digital converter, a digital interpolation circuit, a phase error circuit, and a phase adjustment control circuit. The analog to digital converter samples an analog data input at a sampling phase governed at least in part by a coarse control, and provides a series of digital samples. The digital interpolation circuit interpolates between a subset of the series of digital samples based at least in part on a fine control. The phase error circuit calculates a phase error value. The phase adjustment control circuit is operable to determine the coarse control and the fine control based at least in part on the phase error value. | 01-27-2011 |

20120075011 | Tunable Biquad Filter Circuit Including Phase Shift Detection and Methods for Using Such - Various embodiments of the present invention provide tunable filter circuits and methods for using such. As an example, a tunable biquad filter is disclosed that includes a tunable biquad circuit, a mixer circuit and a low pass filter. The tunable biquad circuit exhibits a cutoff frequency corresponding to an adjustment value, and is operable to receive an filter input and to provide a filter output. The mixer circuit is operable to provide a product of the filter input and the filter output. The product includes a time dependent component and a static component. The low pass filter is operable to receive the product and to provide the static component. | 03-29-2012 |

20120075012 | Systems and Methods for Filter Initialization and Tuning - Various embodiments of the present invention provide systems and methods for data filter tuning. As an example, a method for filter tuning is disclosed that includes: providing a tunable filter having an operation filter and a calibration filter; applying a low frequency test input to the operation filter in place of an input signal to yield a first filter output; calculating a low frequency magnitude value corresponding to the first filter output; applying a high frequency test input to the operation filter in place of an input signal to yield a second filter output; calculating a high frequency magnitude value corresponding to the second filter output; modifying a tuning factor of the calibration filter when a ratio of the high frequency magnitude value and the low frequency magnitude value is outside of a defined range; and storing the tuning factor of the calibration filter when the ratio of the high frequency magnitude value and the low frequency magnitude value is within the defined range. | 03-29-2012 |

20120075131 | Systems and Methods for Enhancing Analog to Digital Conversion Resolution - Various embodiments of the present invention provide systems and methods for analog to digital conversion. As an example, a circuit for converting analog signals to digital signals is disclosed. The circuit includes a variable gain amplifier circuit, an analog to digital converter circuit, and a summation circuit. The variable gain amplifier circuit is operable to apply a first gain value to an input to yield a first amplified output, and to apply a second gain value to the input to yield a second amplified output. The analog to digital converter circuit is operable to receive a derivative of the first amplified output and to provide a corresponding first digital sample, and to receive a derivative of the second amplified output and to provide a corresponding second digital sample. The summation circuit is operable to combine the first digital sample and the second digital sample. | 03-29-2012 |

20130234874 | Digital-to-Analog Converter - A digital-to-analog converter (DAC) has a pulse-width encoder that generates a charging pulse having a pulse width proportional to the DAC's digital input value. The charging pulse controls a charging switch that selectively connects a current source to a capacitor for the duration of the charging pulse. At the end of the charging pulse, a voltage corresponding to the charge stored in the capacitor forms the DAC's analog output signal. Such DACs can be configured (1) with negative-gain amplifiers across the capacitor to form a negative feedback loop, (2) with multiple parallel current sources, and/or (3) in differential architectures. | 09-12-2013 |