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Jahnes, NJ

Christopher Jahnes, Upper Saddle River, NJ US

Patent application numberDescriptionPublished
20090258455METHOD OF MINIMIZING BEAM BENDING OF MEMS DEVICE BY REDUCING THE INTERFACIAL BONDING STRENGTH BETWEEN SACRIFICIAL LAYER AND MEMS STRUCTURE - The beam bending of a MEMS device is minimized by reducing interfacial strength between a sacrificial layer and a MEMS structure.10-15-2009
20090324162CMOS COMPATIBLE INTEGRATED DIELECTRIC OPTICAL WAVEGUIDE COUPLER AND FABRICATION - An optoelectronic circuit fabrication method and integrated circuit apparatus fabricated therewith. Integrated circuits are fabricated with an integral optical coupling transition to efficiently couple optical energy from an optical fiber to an integrated optical waveguide on the integrated circuit. Layers of specific materials are deposited onto a semiconductor circuit to support etching of a trench to receive an optical coupler that performs proper impedance matching between an optical fiber and an on-circuit optical waveguide that extends part way into the transition channel. A silicon based dielectric that includes at least a portion with a refractive index substantially equal to a section of the optical fiber is deposited into the etched trench to create the optical coupler. Silicon based dielectrics with graded indices are also able to be used. Chemical mechanical polishing is used finalize preparation of the optical transition and integrated circuit.12-31-2009

Patent applications by Christopher Jahnes, Upper Saddle River, NJ US

Christopher V. Jahnes, Upper Saddle River, NJ US

Patent application numberDescriptionPublished
20090194502AMORPHOUS NITRIDE RELEASE LAYERS FOR IMPRINT LITHOGRAPHY, AND METHOD OF USE - A morphous inorganic nitrides are used as release layers on templates for nanoimprint lithography. Such a layer facilitates the release of a template from a cured, hardened composition into which the template has transferred a pattern, by reducing the adhesion energy between the release layer and the cured, hardened composition. The release layer may include one or more metallic or semiconductor elements such as Al, Mn, B, Co, Ti, Ta, W and Ge.08-06-2009
20090263991Negative Thermal Expansion System (NTES) Device for TCE Compensation in Elastomer Compsites and Conductive Elastomer Interconnects in Microelectronic Packaging - A method for fabricating a negative thermal expanding system device includes coating a wafer with a thermally decomposable polymer, patterning the decomposable polymer into repeating disk patterns, releasing the decomposable polymer from the wafer and forming a sheet of repeating patterned disks, suspending the sheet into a first solution with seeding compounds for electroless decomposition, removing the sheet from the first solution, suspending the sheet into a second solution to electrolessly deposit a first layer material onto the sheet, removing the sheet from the second solution, suspending the sheet into a third solution to deposit a second layer of material having a lower TCE value than the first layer of material, separating the patterned disks from one another, and annealing thermally the patterned disks to decompose the decomposable polymer and creating a cavity in place of the decomposable polymer.10-22-2009
20110034047Negative Thermal Expansion System (NTES) Device for TCE Compensation in Elastomer Composites and Conductive Elastomer Interconnects in Microelectronic Packaging - A method for fabricating a negative thermal expanding system device includes coating a wafer with a thermally decomposable polymer, patterning the decomposable polymer into repeating disk patterns, releasing the decomposable polymer from the wafer and forming a sheet of repeating patterned disks, suspending the sheet into a first solution with seeding compounds for electroless decomposition, removing the sheet from the first solution, suspending the sheet into a second solution to electrolessly deposit a first layer material onto the sheet, removing the sheet from the second solution, suspending the sheet into a third solution to deposit a second layer of material having a lower TCE value than the first layer of material, separating the patterned disks from one another, and annealing thermally the patterned disks to decompose the decomposable polymer and creating a cavity in place of the decomposable polymer.02-10-2011
20110315526PLANAR CAVITY MEMS AND RELATED STRUCTURES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES - A method of forming a Micro-Electro-Mechanical System (MEMS) includes forming a lower electrode on a first insulator layer within a cavity of the MEMS. The method further includes forming an upper electrode over another insulator material on top of the lower electrode which is at least partially in contact with the lower electrode. The forming of the lower electrode and the upper electrode includes adjusting a metal volume of the lower electrode and the upper electrode to modify beam bending.12-29-2011
20110315527PLANAR CAVITY MEMS AND RELATED STRUCTURES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES - Planar cavity Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structure are provided. The method includes forming at least one Micro-Electro-Mechanical System (MEMS) cavity having a planar surface using a reverse damascene process.12-29-2011
20110316097PLANAR CAVITY MEMS AND RELATED STRUCTURES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES - A method of forming at least one Micro-Electro-Mechanical System (MEMS) cavity includes forming a first sacrificial cavity layer over a wiring layer and substrate. The method further includes forming an insulator layer over the first sacrificial cavity layer. The method further includes performing a reverse damascene etchback process on the insulator layer. The method further includes planarizing the insulator layer and the first sacrificial cavity layer. The method further includes venting or stripping of the first sacrificial cavity layer to a planar surface for a first cavity of the MEMS.12-29-2011
20110318861PLANAR CAVITY MEMS AND RELATED STRUCTURES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES - A method of forming at least one Micro-Electro-Mechanical System (MEMS) cavity includes forming a first sacrificial cavity layer over a lower wiring layer. The method further includes forming a layer. The method further includes forming a second sacrificial cavity layer over the first sacrificial layer and in contact with the layer. The method further includes forming a lid on the second sacrificial cavity layer. The method further includes forming at least one vent hole in the lid, exposing a portion of the second sacrificial cavity layer. The method further includes venting or stripping the second sacrificial cavity layer such that a top surface of the second sacrificial cavity layer is no longer touching a bottom surface of the lid, before venting or stripping the first sacrificial cavity layer thereby forming a first cavity and second cavity, respectively.12-29-2011

Patent applications by Christopher V. Jahnes, Upper Saddle River, NJ US

Christopher V. Jahnes, Saddle River, NJ US

Patent application numberDescriptionPublished
20120001166PARELLEL OPTICAL TRANSCEIVER MODULE - A silicon-on-insulator wafer is provided. The silicon-on-insulator wafer includes a silicon substrate having optical vias formed therein. In addition, an optically transparent oxide layer is disposed on the silicon substrate and the optically transparent oxide layer is in contact with the optical vias. Then, a complementary metal-oxide-semiconductor layer is formed over the optically transparent oxide layer.01-05-2012

Christopher Vincent Jahnes, Upper Saddle River, NJ US

Patent application numberDescriptionPublished
20090001587Ta-TaN SELECTIVE REMOVAL PROCESS FOR INTEGRATED DEVICE FABRICATION - Disclosed are a method and a system for processing a semiconductor structure of the type including a substrate, a dielectric layer, and a TaN—Ta liner on the dielectric layer. The method comprises the step of using XeF2 to remove at least a portion of the TaN—Ta liner completely to the dielectric layer. In the preferred embodiments, the present invention uses XeF2 selective gas phase etching as alternatives to Ta—TaN Chemical Mechanical Polishing (CMP) as a basic “liner removal process” and as a “selective cap plating base removal process.” In this first use, XeF2 is used to remove the metal liner, TaN—Ta, after copper CMP. In the second use, the XeF2 etch is used to selectively remove a plating base (TaN—Ta) that was used to form a metal cap layer over the copper conductor.01-01-2009
20090091037Methods for Fabricating Contacts to Pillar Structures in Integrated Circuits - A pillar structure that is contacted by a vertical contact is formed in an integrated circuit. A hard mask is formed and utilized to pattern a least a portion of the pillar structure. The hard mask comprises carbon. Subsequently, the hard mask is removed. A conductive material is then deposited in a region previously occupied by the hard mask to form the vertical contact. The hard mask may, for example, comprise diamond-like carbon. The pillar structure may have a width or diameter less than about 100 nanometers.04-09-2009
20090108381Low temperature bi-CMOS compatible process for MEMS RF resonators and filters - A method of formation of a microelectromechanical system (MEMS) resonator or filter which is compatible with integration with any analog, digital, or mixed-signal integrated circuit (IC) process, after or concurrently with the formation of the metal interconnect layers in those processes, by virtue of its materials of composition, processing steps, and temperature of fabrication is presented. The MEMS resonator or filter incorporates a lower metal level, which forms the electrodes of the MEMS resonator or filter, that may be shared with any or none of the existing metal interconnect levels on the IC. It further incorporates a resonating member that is comprised of at least one metal layer for electrical connection and electrostatic actuation, and at least one dielectric layer for structural purposes. The gap between the electrodes and the resonating member is created by the deposition and subsequent removal of a sacrificial layer comprised of a carbon-based material. The method of removal of the sacrificial material is by an oxygen plasma or an anneal in an oxygen containing ambient. A method of vacuum encapsulation of the MEMS resonator or filter is provided through means of a cavity containing the MEMS device, filled with additional sacrificial material, and sealed. Access vias are created through the membrane sealing the cavity; the sacrificial material is removed as stated previously, and the vias are re-sealed in a vacuum coating process.04-30-2009
20100276786Through Substrate Vias - Methods and apparatus for forming through-vias are presented, for example, a method for forming a via in a portion of a semiconductor wafer comprising a substrate. The method comprises forming a trench surrounding a first part of the substrate such that the first part is separated from a second part of the substrate, forming a hole through the substrate within the first part, and forming a first metal within the hole. The trench extends through the substrate. The first metal extends from a front surface of the substrate to a back surface of the substrate. The via comprises the hole and the first metal.11-04-2010

Patent applications by Christopher Vincent Jahnes, Upper Saddle River, NJ US

Christopher Vincent Jahnes, Bergen County, NJ US

Patent application numberDescriptionPublished
20110109405Low Temperature BI-CMOS Compatible Process For MEMS RF Resonators and Filters - A microelectromechanical system (MEMS) resonator or filter including a first conductive layer, one or more electrodes patterned in the first conductive layer which serve the function of signal input, signal output, or DC biasing, or some combination of these functions, an evacuated cavity, a resonating member comprised of a lower conductive layer and an upper structural layer, a first air gap between the resonating member and one or more of the electrodes, an upper membrane covering the cavity, and a second air gap between the resonating member and the upper membrane.05-12-2011