Patent application number | Description | Published |
20090091483 | FLASH ANALOG TO DIGITAL CONVERTER (ADC) - A flash ADC in which different thresholds are provided to different comparators in different time instances. Such a feature may be advantageously used in digital converters type components since the flash ADC would provide more time for amplifiers to generate amplified residue signals. | 04-09-2009 |
20090091487 | Spurious Free Dynamic Range Of An Analog To Digital Converter - Removing an Nth harmonic (of a fundamental frequency) generated due to non-ideal ADC operation from the output of the ADC. In an embodiment, digital values containing in-phase and quadrature phase components of the Nth harmonic are generated using mathematical operations, scaled using scaling factors, and then subtracted from the (non-ideal) output of the ADC. A continuous-time derivative of the input signal used to generate the quadrature phase component, enabling a same set of scaling factors to be used for the same input irrespective of the sampling frequency. Spurious Free Dynamic Range of the ADC is thus improved. | 04-09-2009 |
20090146857 | Maintaining A Reference Voltage Constant Against Load Variations - A voltage source providing a constant reference voltage, independent of load variations at an output terminal. The effective impedance (looking-in impedance) at the output terminal is designed to be independent of frequency of the signals at the output terminal. In an embodiment, the resistance of one of two parallel impedance paths constituting the effective impedance is made equal to the resistance of the other path, and the time constants of both paths are made equal. As a result, the effective impedance is made independent of frequency, and the strength of the reference voltage is maintained constant without exhibiting ringing, DC droop, etc., despite load variations. | 06-11-2009 |
20100052741 | DUAL INTEGRATOR CIRCUIT FOR ANALOG FRONT END (AFE) - A circuit includes a generating circuit that generates a current signal in response to an input signal, a first one of a plurality of integrators that generates a voltage signal from the current signal, a comparator that is responsive to the voltage signal to compare the voltage signal with a predefined voltage, a switching circuit that reconfigures a first capacitor and a second capacitor connected to the first one of the plurality of integrators to discharge the first capacitor and to enable the second capacitor to generate the voltage signal in response to the current signal, and an analog-to-digital converter to generate an output when a predefined time interval has elapsed. The output is obtained by adding a first charge value corresponding to a count of number of times the voltage signal reaches the predefined voltage in the predefined time interval and a second charge value from the analog-to-digital converter. | 03-04-2010 |
20100080083 | Time-Dependant Gain Control For An Amplifier Used In Receiving Echoes - An amplifier circuit to amplify a sequence of echoes and to generate a corresponding sequence of amplified signals. In an embodiment, the amplifier includes an operational amplifier, with variable input and feedback resistances such that the ratio of the two resistances can be controlled. A gain control block controls the ratio in a time dependent manner to obtain desired gain factors for each of the echoes. The gain factors can be pre-computed such that all the echoes are gained to the same level in case of an ultra-sound system. | 04-01-2010 |
20100148838 | WIDE RANGE DELAY CELL - A delay cell with a wider delay range is provided. The delay cell employs frequency dependent current source to generate the majority of the delay of the cell, while a control circuit (which is generally a current source that is controlled by a control voltage) provides additional delay. Thus, the delay cell provided here can be used to improve the performance of delay locked loops (DLLs) and other circuits. | 06-17-2010 |
20100309033 | CORRECTION OF SAMPLING MISMATCH IN TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTERS - A time-interleaved analog-to-digital converter (ADC) is provided. The ADC generally comprises a first ADC, a second ADC, correction circuit, a divider, and a clocking circuit. The first ADC receives an analog input signal and generates a first output and a differentiated output. The second ADC receives the analog input signal and generates a second output. The correction circuit receives the first output, the second output, and the differentiated output and generates a first error signal and a second error signal. The divider receives the first error signal and the second error signal and generates a timing error by dividing the second error signal by the first error signal, and the clocking circuit receives a clock signal and the timing error and generates a plurality of corrected clocking signals, where each of the first and second ADCs receives at least one of the clocking signals. | 12-09-2010 |
20110012764 | MULTIBIT RECYCLIC PIPELINED ADC ARCHITECTURE - An apparatus is provided. The apparatus comprises a sample switch, a sampling capacitor, an amplifier, feedback branches, a second hold switch, an N-bit converter pair, a third hold switch, and an M-bit converter pair. The sample receives an input signal and is actuated by a sample signal. The sampling capacitor is coupled to the sample switch. The amplifier has a first input terminal that is coupled to the sampling capacitor. The feedback branches are coupled between the output terminal of the amplifier and the first input terminal of the amplifier, with each feedback branch including a feedback capacitor, and a first hold switch that is coupled to the feedback capacitor. The second hold switch is coupled to the sampling switch. The N-bit converter pair is coupled to the sampling switch and to the second hold switch. The third hold switch is coupled to at least one of the feedback branches, and the M-bit converter pair is coupled to the output terminal of the amplifier and to the third hold switch. | 01-20-2011 |
20130021018 | Ambient Noise Cancellation in Pulsed Input System - Embodiments of the invention provide a pulseoximetry system with ambient offset cancellation that subtracts an estimated ambient offset to thereby allow a large front end gain while operating the front end on a low supply voltage. This large gain reduces input referred noise of an analog to digital converter in the front end while providing high dynamic range for signals with a large ambient offset. | 01-24-2013 |
20130021185 | Low Noise Front End For Pulsed Input System - Embodiments of the invention provide a pulsed signal detection system with reduced noise bandwidth in the frontend. Analog to digital conversion speed is decoupled from the pulsed duty cycle timing. This in turn reduces the power consumption of the ADC and the front end while providing a high dynamic range. The ADC may be a continuous time sigma delta converter to reduce the drive requirements of the front end. | 01-24-2013 |