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| 20100320545 | PLANAR AND NON-PLANAR CMOS DEVICES WITH MULTIPLE TUNED THRESHOLD VOLTAGES - A semiconductor structure is provided that includes a first device region including a first threshold voltage adjusting layer located atop a semiconductor substrate, a gate dielectric located atop the first threshold voltage adjusting layer, and a gate conductor located atop the gate dielectric. The structure further includes a second device region including a gate dielectric located atop the semiconductor substrate, and a gate conductor located atop the gate dielectric; and a third device region including a gate dielectric located atop the semiconductor substrate, a second threshold voltage adjusting layer located atop the gate dielectric, and a gate conductor located atop the second threshold voltage adjusting layer. In the inventive structure the first threshold voltage adjusting layer includes one of an nFET threshold voltage adjusting material or a pFET threshold voltage adjusting material and the second threshold voltage adjusting layer is the other of the nFET threshold voltage adjusting material or the pFET threshold voltage adjusting material. | 12-23-2010 |
| 20110081754 | METHODS FOR OBTAINING GATE STACKS WITH TUNABLE THRESHOLD VOLTAGE AND SCALING - Methods of forming complementary metal oxide semiconductor (CMOS) structures with tunable threshold voltages are provided. The methods disclose a technique of obtaining selective placement of threshold voltage adjusting materials on a semiconductor substrate by using a block mask prior to deposition of the threshold voltage adjusting materials. The block mask is subsequently removed to obtain a patterned threshold voltage adjusting material on the semiconductor substrate. The methods are material independent and can be used in sequence for both nFET threshold voltage adjusting materials and pFET threshold voltage adjusting materials. | 04-07-2011 |
| 20110081765 | METHOD TO IMPROVE WET ETCH BUDGET IN FEOL INTEGRATION - A method of forming a semiconductor device is provided where in one embodiment an STI fill is recessed below the pad nitride and pad oxide layers, to a level substantially coplanar with the top surface of the substrate. A thin (having a thickness in the range of about 10 Å-100 Å) wet etch resistant layer is formed in contact with and completely covering at least the top surface of the recessed STI fill material. The thin wet etch resistant layer is more resistant to a wet etch process than at least the pad oxide layer. The thin wet etch resistant layer may be a refractory dielectric material, or a dielectric such as HfO | 04-07-2011 |
| 20110108921 | SINGLE METAL GATE CMOS INTEGRATION BY INTERMIXING POLARITY SPECIFIC CAPPING LAYERS - A method for forming a complementary metal oxide semiconductor device includes forming a first capping layer on a dielectric layer, blocking portions in the capping layer in regions where the capping layer is to be preserved using a block mask. Exposed portions of the first capping layer are intermixed with the dielectric layer to form a first intermixed layer. The block mask is removed. The first capping layer and the first intermixed layer are etched such that the first capping layer is removed to re-expose the dielectric layer in regions without removing the first intermixed layer. | 05-12-2011 |
| 20110115026 | CONTROL OF THRESHOLD VOLTAGES IN HIGH-K METAL GATE STACK AND STRUCTURES FOR CMOS DEVICES - A high-k metal gate stack and structures for CMOS devices and a method for forming the devices. The gate stack includes a germanium (Ge) material layer formed on the semiconductor substrate, a diffusion barrier layer formed on the Ge material layer, a high-k dielectric having a high dielectric constant greater than approximately 3.9 formed over the diffusion barrier layer, and a conductive electrode layer formed above the high-k dielectric layer. | 05-19-2011 |
| 20110115027 | STRUCTURE AND METHOD TO OBTAIN EOT SCALED DIELECTRIC STACKS - Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer. | 05-19-2011 |
| 20110212548 | METHOD FOR SEMICONDUCTOR GATE HARDMASK REMOVAL AND DECOUPLING OF IMPLANTS - A method is provided for fabricating a semiconductor device having implanted source/drain regions and a gate region, the gate region having been masked by the gate hardmask during source/drain implantation, the gate region having a polysilicon gate layered on a metal layered on a high-K dielectric layer. The gate region and the source/drain regions may be covered with a self planarizing spin on film. The film may be blanket etched back to uncover the gate hardmask while maintaining an etched back self planarizing spin on film on the implanted source/drain regions. The gate hardmask may be etched back while the etched back film remains in place to protect the implanted source/drain regions. The gate region may be low energy implanted to lower sheet resistance of the polysilicon layer. The etched back film may be then removed. | 09-01-2011 |
| 20110260257 | High Performance Non-Planar Semiconductor Devices with Metal Filled Inter-Fin Gaps - A non-planar semiconductor transistor device includes a substrate layer. Conductive channels extend between corresponding source and drain electrodes. A gate stack extending in a direction perpendicular to the conductive channels crosses over the plurality of conductive channels. The gate stack includes a dielectric layer running along the substrate and the plurality of conductive channels and arranged with a substantially uniform layer thickness, a work-function electrode layer covers the dielectric layer and is arranged with a substantially uniform layer thickness, and a metal layer, distinct from the work-function electrode layer, covers the work-function electrode layer and is arranged with a substantially uniform height with respect to the substrate such that the metal layer fills a gap between proximate conductive channels of the plurality of conductive channels. | 10-27-2011 |
| 20110303981 | Scheme to Enable Robust Integration of Band Edge Devices and Alternatives Channels - A method of forming a semiconductor device includes forming a buried oxide (BOX) layer on a semiconductor substrate, forming a silicon-on-insulator (SOI) layer on the BOX layer, depositing a hard mask including one of silicon, a nitride, and a metal oxide on the SOI layer, removing the hard mask from a first region of the semiconductor device, performing a cleaning process on the semiconductor device, wherein the hard mask is not removed from a second region of the semiconductor device by the cleaning process, epitaxially growing a semiconductor material in the first region of the semiconductor device, and removing the hard mask from the second region of the semiconductor device. | 12-15-2011 |
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| 20100308412 | CONTROL OF FLATBAND VOLTAGES AND THRESHOLD VOLTAGES IN HIGH-K METAL GATE STACKS AND STRUCTURES FOR CMOS DEVICES - A high-k metal gate stack and structures for CMOS devices and a method for forming the devices. The gate stack includes a high-k dielectric having a high dielectric constant greater than approximately 3.9, a germanium (Ge) material layer interfacing with the high-k dielectric, and a conductive electrode layer disposed above the high-k dielectric or the Ge material layer. The gate stack optimizes a shift of the flatband voltage or the threshold voltage to obtain high performance in p-FET devices. | 12-09-2010 |
| 20110248326 | STRUCTURE AND METHOD TO INTEGRATE EMBEDDED DRAM WITH FINFET - A transistor includes a first fin structure and at least a second fin structure formed on a substrate. A deep trench area is formed between the first and second fin structures. The deep trench area extends through an insulator layer of the substrate and a semiconductor layer of the substrate. A high-k metal gate is formed within the deep trench area. A polysilicon layer is formed within the deep trench area adjacent to the metal layer. The polysilicon layer and the high-k metal layer are recessed below a top surface of the insulator layer. A poly strap in the deep trench area is formed on top of the high-k metal gate and the polysilicon material. The poly strap is dimensioned to be below a top surface of the first and second fin structures. The first fin structure and the second fin structure are electrically coupled to the poly strap. | 10-13-2011 |
| 20110303983 | FINFET DEVICES AND METHODS OF MANUFACTURE - A finFET structure and method of manufacture such structure is provided with lowered Ceff and enhanced stress. The finFET structure includes a plurality of finFET structures and a stress material forming part of a gate stack and in a space between adjacent ones of the plurality of finFET structures. | 12-15-2011 |
| 20120018730 | STRUCTURE AND METHOD FOR STRESS LATCHING IN NON-PLANAR SEMICONDUCTOR DEVICES - Techniques are discloses to apply an external stress onto the source/drain semiconductor fin sidewall areas and latch the same onto the semiconductor fin before releasing the sidewalls for subsequent salicidation and contact formation. In particular, the present disclosure provides methods in which selected portions of a semiconductor are subjected to an amorphizing ion implantation which disorients the crystal structure of the selected portions of the semiconductor fins, relative to portions of the semiconductor fin that is beneath a gate stack and encapsulated with various liners. At least one stress liner is formed and then stress memorization occurs by performing a stress latching annealing. During this anneal, recrystallization of the disoriented crystal structure occurs. The at least one stress liner is removed and thereafter merging of the semiconductor fins in the source/drain regions is performed. | 01-26-2012 |
| 20120018813 | BARRIER COAT FOR ELIMINATION OF RESIST RESIDUES ON HIGH k/METAL GATE STACKS - A technique for substantially eliminating resist residues from a gate stack that includes, from bottom to top, a high k gate dielectric and a metal gate, e.g., a high k/metal gate stack, is provided. In particular and in one embodiment, a method is disclosed in which a patterned resist and optionally a patterned barrier coating are formed atop a surface of the metal gate electrode of a high k/metal gate stack prior to patterning the metal gate electrode. At least the metal gate electrode not protected by the patterned material is then etched. The presence of the barrier coating eliminates resist residues from the resultant gate stack. The technique provided can be used in fabricating planar semiconductor devices such as, for example, metal oxide semiconductor field effect transistors (MOSFETS) including complementary metal oxide semiconductor (CMOS) field effect transistors, as well as non-planar semiconductor devices such as, for example, finFETs. | 01-26-2012 |
| 20120037999 | DIFFERENTIAL STOICHIOMETRIES BY INFUSION THRU GCIB FOR MULTIPLE WORK FUNCTION METAL GATE CMOS - A method of modulating the work function of a metal layer in a localized manner is provided. Metal gate electrodes having multiple work functions may then be formed from this metal layer. Although the metal layer and metal gate electrodes over both the nFET and pFET regions of the instant substrates are made from only a single metal, they exhibit different electrical performances. The variation of electrical performances is achieved by infusing stoichiometrically-altering atoms into the metal layer, from which the metal gate electrodes are made, via a Gas Cluster Ion Beam process. The resulting metal gate electrodes have the necessary threshold voltages for both nFET and pFET, and are ideal for use in CMOS devices. | 02-16-2012 |
| 20120040522 | METHOD FOR INTEGRATING MULTIPLE THRESHOLD VOLTAGE DEVICES FOR CMOS - A method to achieve multiple threshold voltage (Vt) devices on the same semiconductor chip is disclosed. The method provides different threshold voltage devices using threshold voltage adjusting materials and a subsequent drive in anneal instead of directly doping the channel. As such, the method of the present disclosure avoids short channel penalties. Additionally, no ground plane/back gates are utilized in the present application thereby the method of the present disclosure can be easily integrated into current complementary metal oxide semiconductor (CMOS) processing technology. | 02-16-2012 |
| 20120074533 | Structures And Techniques For Atomic Layer Deposition - In one exemplary embodiment, a method includes: forming at least one first monolayer of first material on a surface of a substrate by performing a first plurality of cycles of atomic layer deposition; thereafter, annealing the formed at least one first monolayer of first material under a first inert atmosphere at a first temperature between about 650° C. and about 900° C.; thereafter, forming at least one second monolayer of second material by performing a second plurality of cycles of atomic layer deposition, where the formed at least one second monolayer of second material at least partially overlies the annealed at least one first monolayer of first material; and thereafter, annealing the formed at least one second monolayer of second material under a second inert atmosphere at a second temperature between about 650° C. and about 900° C. | 03-29-2012 |
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| 20110106701 | METHOD AND APPARATUS FOR PERFORMING VOICE-BASED CREDIT CARD PROCESSING - One embodiment of the present invention provides a system for performing voice-based credit card processing. During operation, the system receives voice input from a merchant at a computer via a telephone to initiate a credit card transaction. Next, the system authenticates the merchant. After authenticating the merchant, the system prompts the merchant for a credit card number. Next, the system authenticates a consumer associated with the credit card. Note that the system can authenticate the consumer with pre-registered information that is associated with the credit card. Once the consumer is authenticated, the system prompts the merchant for a transaction amount. Next, the system receives the transaction amount from the merchant. The system then authorizes the credit card transaction for the transaction amount. Finally, the system reports the result of the authorization to the merchant. Note that embodiments of the present invention enable the merchant to process credit card transactions at reduced cost without the need for any equipment other than a telephone, thus providing the ability to have instant credit card enabled merchants on demand. | 05-05-2011 |
| 20110246209 | METHOD AND SYSTEM FOR PREDICTING CUSTOMER FLOW AND ARRIVAL TIMES USING POSITIONAL TRACKING OF MOBILE DEVICES - A method and system for predicting customer flow and arrival times using positional tracking of mobile devices whereby data associated with one or more participating businesses is obtained including, but not limited to, the business name and the business location. The positions of one or more mobile devices associated with one or more consumers are tracked and an estimated direction/path and speed of the one or more consumers is thereby determined. A probability that the one or more consumers will utilize a particular participating business and/or products/services associated with a participating business, is then determined and the estimated arrival times at the particular participating business of consumers deemed probable to utilize the particular participating business is calculated. Data representing the number of consumers deemed probable to utilize the particular participating business and/or the estimated arrival times at the particular participating business of consumers deemed probable to utilize the particular participating business is then provided to the particular participating business. | 10-06-2011 |
| 20110246304 | METHOD AND SYSTEM FOR PROVIDING TARGETED ADVERTISEMENTS BASED ON POSITIONAL TRACKING OF MOBILE DEVICES AND FINANCIAL DATA - A method and system for providing targeted advertisements based on positional tracking of mobile devices and financial data whereby data associated with one or more participating businesses is obtained including, but not limited to, the business name and the business location. A mobile device associated with a consumer is associated with financial data associated with the consumer and the position of the mobile device associated with the consumer is tracked. A probability that the consumer will respond to an offer or advertisement for a particular participating business, and/or specific products and/or services associated with a particular participating business, is then determined for the consumer based, at least in part on the financial data associated with the consumer. The consumer's estimated arrival time at a defined point in the vicinity of the particular participating business is then calculated and the participating business is provided the opportunity to send the consumer one or more offers and/or information regarding the participating business in relative “real-time”. | 10-06-2011 |
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| 20080298444 | Dsl System - Methods, techniques, computer program products, apparatus, devices, etc., used in connection with DSL Management Interfaces, significantly improve the management capabilities of a DSL network and/or improve testing relating to DSL equipment and services by permitting better control and operation of a DSL system, including implementation of timestamping for more accurate measurement, monitoring and control of a system. Timestamping further allows customized data collection techniques, where a DSL line can be measured or monitored at intervals whose frequency depends on the line's stability. Moreover, data parameter read and control parameter write operations are presented in conjunction with the use of timestamping. Also, control and operation of a DSL system is enhanced by implementing bit-loading that minimizes, eliminates or otherwise mitigates the amount by which the SNR margin per tone exceeds a maximum SNR margin quantity, where such bit-loading can be selected through an appropriate interface. | 12-04-2008 |
| 20090323903 | METHOD AND APPARATUS FOR ANALYZING AND MITIGATING NOISE IN A DIGITAL SUBSCRIBER LINE - Data indicative of a level of stability of a DSL link is received. Based on the received data, it is determined whether the data indicates a level of stability of the DSL link that is above or below a minimum threshold. If the level of stability of the DSL link is below the minimum threshold, die noise associated with the DSL link before the time of failure is compared with the noise associated with the DSL link after the time of failure. If the difference between the noise before and after the time of failure exceeds a threshold, then the difference in noise is characterized as a stationary noise associated with the DSL link. However, if the difference between the noise before and after the time of failure is below the threshold, a determination is made whether the failure is associated with a loss of power to the DSL link or a severe impulse noise event—the difference in noise is characterized accordingly. Finally, the characterization of the noise associated with the DSL link is preserved for subsequent possible reconfiguration of the DSL link to improve link stability. | 12-31-2009 |
| 20100074312 | HIGH SPEED MULTIPLE USER MULTIPLE LOOP DSL SYSTEM - A high speed multiple user multiple-loop DSL system is described. In one embodiment, it includes a first DSL loop to carry DSL traffic to a first user and a second DSL loop to carry DSL traffic to a second user. A first junction connects the traffic of the first DSL loop to a third DSL loop, and a second junction connects the traffic of the second DSL loop to the third DSL loop. | 03-25-2010 |
| 20100135482 | INTERFERENCE CANCELLATION SYSTEM - An adaptive interference cancellation system is described. In one example the system operates by receiving a data signal using a DSL (Digital Subscriber Line) and receiving a reference signal, the reference signal corresponding, in part, to noise on the data signal. The reference signal is classified and a noise cancellation signal is applied to the data signal based on the classification. | 06-03-2010 |
| 20110299579 | DSL SYSTEM - Methods, techniques, computer program products, apparatus, devices, etc., used in connection with DSL Management Interfaces, significantly improve the management capabilities of a DSL network and/or improve testing relating to DSL equipment and services by permitting better control and operation of a DSL system, including implementation of timestamping for more accurate measurement, monitoring and control of a system. Timestamping further allows customized data collection techniques, where a DSL line can be measured or monitored at intervals whose frequency depends on the line's stability. Moreover, data parameter read and control parameter write operations are presented in conjunction with the use of timestamping. Also, control and operation of a DSL system is enhanced by implementing bit-loading that minimizes, eliminates or otherwise mitigates the amount by which the SNR margin per tone exceeds a maximum SNR margin quantity, where such bit-loading can be selected through an appropriate interface. | 12-08-2011 |
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| 20090157476 | MARKETING CAMPAIGN MANAGEMENT - A device receives one or more of customer data, customer models, or customer reports, calculates scored information based on the one or more of the customer data, customer models, or customer reports, and generates marketing campaign information for a product or a service based on the scored information and the one or more of the customer data, customer models, or customer reports. The device also generates a customer list based on the marketing campaign information and the one or more of the customer data, customer models, or customer reports, and conveys the marketing campaign information to one or more customers on the customer list. | 06-18-2009 |
| 20090158272 | CONFIGURATION MANAGEMENT CENTER - A device receives configuration information associated with software to be installed in a network, builds a software package based on the configuration information, determines one or more devices of the network to perform installation of the software package, sends a command, to perform installation of the software package, to the determined one or more devices, receives one or more software package installation results from one or more other devices of the network where the software package is installed, and generates one or more reports based on the one or more software package installation results. | 06-18-2009 |
