Patent application number | Description | Published |
20100144141 | Semiconductor Device and Method of Forming the Same - Provided are a semiconductor device and a method of forming the semiconductor device. The method may include forming a semiconductor pattern on a substrate, forming an interlayer insulating layer including an opening exposing the semiconductor pattern, forming a semiconductor ohmic pattern on the semiconductor pattern, forming an electrode ohmic layer on the semiconductor ohmic pattern, performing a wet etching on the electrode ohmic layer, and forming an electrode pattern on the etched electrode ohmic layer. | 06-10-2010 |
20100203672 | METHODS OF MANUFACTURING PHASE CHANGE MEMORY DEVICES - A phase change memory is manufactured by providing a substrate including a layer of phase-change material, forming a damascene pattern on the layer of phase-change material, and forming both a top electrode and a bit line in the damascene pattern. | 08-12-2010 |
20110207285 | Method Of Forming Pattern Structure And Method Of Fabricating Semiconductor Device Using The Same - A method of forming a pattern structure and a method of fabricating a semiconductor device using the pattern structure, are provided the method of forming the pattern structure includes forming a mask on an underlying layer formed on a lower layer. The underlying layer is etched using the mask as an etching mask, thereby forming patterns on the lower layer. The patterns define at least one opening. A sacrificial layer is formed in the opening and the mask is removed. The sacrificial layer in the opening is partially etched when the mask is removed. | 08-25-2011 |
20110248235 | VARIABLE RESISTANCE MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME - A nonvolatile memory device includes a substrate and a first insulating layer on the substrate. The first insulating layer includes a first opening therein. A lower electrode is provided in the first opening and protrudes from a surface of the first insulating layer outside the first opening. An electrode passivation pattern is provided on a sidewall of the lower electrode that protrudes from the surface of the first insulating layer. A second insulating layer is provided on the first insulating layer and includes a second opening therein at least partially exposing the lower electrode. A variable resistance material layer extends into the second opening to contact the lower electrode. The electrode passivation layer electrically separates the sidewall of the lower electrode from the variable resistance material layer. The electrode passivation pattern is formed of a material having an etching selectivity to that of the second insulating layer. Related fabrication methods are also discussed. | 10-13-2011 |
20110263093 | Methods of Forming Variable-Resistance Memory Devices and Devices Formed Thereby - Methods of forming a variable-resistance memory device include patterning an interlayer dielectric layer to define an opening therein that exposes a bottom electrode of a variable-resistance memory cell, on a memory cell region of a substrate (e.g., semiconductor substrate). These methods further include depositing a layer of variable-resistance material (e.g., phase-changeable material) onto the exposed bottom electrode in the opening and onto a first portion of the interlayer dielectric layer extending opposite a peripheral circuit region of the substrate. The layer of variable-resistance material and the first portion of the interlayer dielectric layer are then selectively etched in sequence to define a recess in the interlayer dielectric layer. The layer of variable-resistance material and the interlayer dielectric layer are then planarized to define a variable-resistance pattern within the opening. | 10-27-2011 |
20120228574 | VARIABLE RESISTIVE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A variable resistive memory device includes a substrate comprising a cell region and a peripheral region, a word line extending in a first direction formed on the substrate of the cell region, a switching element formed on the word line, a variable resistance layer formed on the word line, and at least one transistor comprising a gate stack, the gate stack formed on the substrate of the peripheral region, wherein the word line comprises a metal layer formed at a same level as the gate stack. | 09-13-2012 |
20120228577 | PHASE CHANGE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A phase change memory device includes a mold oxide layer on a substrate, a lower electrode on the mold oxide layer and connected to the substrate, a blocking structure covering a part of the lower electrode and including an etch-stop layer and a blocking structure insulating layer, and a phase change layer covering a remaining part of the lower electrode not covered by the blocking structure, The etch-stop layer includes a material having a higher etching selectivity than that of the lower electrode. | 09-13-2012 |
20150039547 | NEUROMOPHIC SYSTEM AND CONFIGURATION METHOD THEREOF - A method of generating neuron spiking pulses in a neuromorphic system is provided which includes floating one or more selected bit lines connected to target cells, having a first state, from among a plurality of memory cells arranged at intersections of a plurality of word lines and a plurality of bit lines; and stepwisely increasing voltages applied to unselected word lines connected to unselected cells, having a second state, from among memory cells connected to the one or more selected bit lines other than the target cells having the first state. | 02-05-2015 |
20150043267 | VARIABLE RESISTANCE MEMORY DEVICE AND A VARIABLE RESISTANCE MEMORY SYSTEM INCLUDING THE SAME - A variable resistance memory system includes a variable resistance memory device including a memory cell array including first and second areas; and a memory controller configured to control the variable resistance memory device. The first area includes first variable resistance memory cells including a first variable resistance material layer and the second area includes second variable resistance memory cells including a second variable resistance material layer having a metallic doping concentration higher than a metallic doping concentration of the first variable resistance material layer. The first variable resistance memory cells are used as storage and the second variable resistance memory cells are used as a buffer memory. | 02-12-2015 |