Patent application number | Description | Published |
20090086525 | Multi-layered memory devices - A multi-layered memory device is provided. The multi-layered memory device includes two or more memory units and an active circuit unit arranged between each of the two or more memory units. The active circuit includes a decoder. Each memory unit includes one or more memory layers. Each memory layer includes a memory array. | 04-02-2009 |
20090283763 | Transistors, semiconductor devices and methods of manufacturing the same - A transistor having a self-align top gate structure and methods of manufacturing the same are provided. The transistor includes an oxide semiconductor layer having a source region, a drain region, and a channel region between the source region and the drain region. The transistor further includes a gate insulating layer and a gate electrode, which are sequentially stacked on the channel region. Semiconductor devices including at least one transistor and methods of manufacturing the same are also provided. | 11-19-2009 |
20090315590 | Logic circuits, inverter devices and methods of operating the same - An inverter device includes at least a first transistor connected between a power source node and ground. The first transistor includes a first gate and a first terminal that are internally capacitive-coupled to control a boost voltage at a boost node. The first terminal is one of a first source and a first drain of the first transistor. | 12-24-2009 |
20090321738 | Display apparatus using oxide diode - Provided may be a display apparatus that uses oxide diodes having a nano rod structure, for example, nano-rod diodes formed of a ZnO group material. The display apparatus may include a substrate, a thin film transistor layer on the substrate, and a light emitting layer on the thin film transistor layer, wherein the light emitting layer may include a plug metal layer on the thin film transistor layer, a plurality of nano-rod diodes vertically formed on the plug metal layer, and a transparent electrode on the nano-rod diodes. | 12-31-2009 |
20100079169 | Inverter, method of operating the same and logic circuit comprising inverter - Provided are an inverter, a method of operating the inverter, and a logic circuit including the inverter. The inverter may include a load transistor and a driving transistor, and at least one of the load transistor and the driving transistor may have a double gate structure. A threshold voltage of the load transistor or the driving transistor may be adjusted by the double gate structure, and accordingly, the inverter may be an enhancement/depletion (E/D) mode inverter. | 04-01-2010 |
20100085821 | Operation method of non-volatile memory - Example embodiments provide a method of operating a non-volatile memory in which the non-volatile memory may only be changed from a first state to a second state and may not be changed from the second state to the first state during a programming operation. | 04-08-2010 |
20100332783 | SEMICONDUCTOR DEVICE HAVING MULTI ACCESS LEVEL AND ACCESS CONTROL METHOD THEREOF - An access control method of a semiconductor device includes providing an inputted password as an input of a hash operator; performing a hash operation in the hash operator and outputting a first hash value; controlling the hash operator so that the hash operation is repeatedly performed in the hash operator by providing the first hash value as an input of the hash operator when the first hash value and a second hash value stored in a nonvolatile memory do not coincide; and setting an access level with respect to the inner circuit according to the repetition number of times of the hash operation of the hash operator when the first and second hash values coincide. | 12-30-2010 |
20110089998 | Logic circuits, inverter devices and methods of operating the same - An inverter device includes at least a first transistor connected between a power source node and ground. The first transistor includes a first gate and a first terminal that are internally capacitive-coupled to control a boost voltage at a boost node. The first terminal is one of a first source and a first drain of the first transistor. | 04-21-2011 |
20110116297 | Multi-layered memory devices - A multi-layered memory device is provided. The multi-layered memory device includes two or more memory units and an active circuit unit arranged between each of the two or more memory units. The active circuit includes a decoder. Each memory unit includes one or more memory layers. Each memory layer includes a memory array. | 05-19-2011 |
20110116336 | Multi-layered memory devices - A multi-layered memory device is provided. The multi-layered memory device includes two or more memory units and an active circuit unit arranged between each of the two or more memory units. The active circuit includes a decoder. Each memory unit includes one or more memory layers. Each memory layer includes a memory array. | 05-19-2011 |
20110175647 | Method of operating inverter - A method of operating inverter may include providing a load transistor and a driving transistor connected to the load transistor wherein at least one of the load transistor and the driving transistor has a double gate structure, and varying a threshold voltage of the at least one of the load transistor and the driving transistor having the double gate structure. A threshold voltage of the load transistor or the driving transistor may be adjusted by the double gate structure, and accordingly, the inverter may be an enhancement/depletion (E/D) mode inverter. | 07-21-2011 |
20140219445 | Processors Including Key Management Circuits and Methods of Operating Key Management Circuits - A system on chip includes a central processing unit and a key manager coupled to the central processing unit. The key manager includes a random number generator configured to generate a key and a key memory configured to store the key and a user setting value associated with the key. | 08-07-2014 |