Patent application number | Description | Published |
20090059682 | SEMICONDUCTOR MEMORY DEVICE HAVING ANTIFUSE CIRCUITRY - A semiconductor memory device includes a fuse box including a plurality of address antifuse circuits, each address antifuse circuit outputting an address fuse signal according to a program state of an antifuse included in the corresponding address antifuse circuit, an address comparator including a plurality of address comparison signal generators, each address comparison signal generator combining a first test signal for determining an initial defect of the antifuse and a corresponding bit of an externally applied address signal to generate a test address, and comparing the test address with the address fuse signal to generate an address comparison signal, and a redundant enable signal generator for enabling a redundancy enable signal in response to a plurality of address comparison signals. | 03-05-2009 |
20100067317 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING SENSE AMPLIFIER OF SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes at least one sense amplifier, a controller and a sense amplifier driver. The sense amplifier includes a PMOS sense amplifier and an NMOS sense amplifier configured to be respectively activated in response to a first supply voltage and a second supply voltage, and to sense and amplify a voltage difference between a corresponding bit line pair. The controller is configured to set an operating mode in response to an external command, to control activation timing of a PMOS drive activation signal and an NMOS drive activation signal according to the set operating mode, and to output the PMOS drive activation signal and the NMOS drive activation signal. The sense amplifier driver is configured to apply the first and second supply voltages to the PMOS and NMOS sense amplifiers, respectively, in response to the PMOS drive activation signal and the NMOS drive activation signal. | 03-18-2010 |
20130100755 | SEMICONDUCTOR MEMORY DEVICE IMPLEMENTING COMPREHENSIVE PARTIAL ARRAY SELF REFRESH SCHEME - A semiconductor memory device performing a comprehensive partial self refresh (CPSR) scheme, in which a CPSR operation of not performing a self refresh operation on the segments included in each bank is disclosed. The semiconductor memory device includes a mask information register configured to generate mask information by storing information indicating a bank and a segment on which the self refresh operation is not performed; and a mask operation circuit configured to not perform the self refresh operation on the segments of each of the banks in response to the mask information. The semiconductor memory device efficiently performs a refresh operation according to user convenience and supports lower power consumption. | 04-25-2013 |
20130176803 | SEMICONDUCTOR MEMORY DEVICE AND REFRESH METHOD THEREOF - A semiconductor memory device and a self-refresh method of the semiconductor memory device. The semiconductor memory device includes: a memory cell array including one or more memory cells; a sense amplifier connected to a sensing line and a complementary sensing line and sensing/amplifying data stored in the one or more memory cells; and a sense amplifier control circuit sequentially supplying a first voltage and a second voltage having different levels to the sense amplifier through the sensing line during a refresh operation. | 07-11-2013 |
20140149652 | MEMORY SYSTEM AND METHOD OF MAPPING ADDRESS USING THE SAME - In one example embodiment, a memory system includes a memory module and a memory controller. The memory module is configured generate density information of the memory module based on a number of the bad pages of the memory module, the bad pages being pages that have a fault. The memory controller is configured to map a continuous physical address to a dynamic random access memory (dram) address of the memory module based on the density information received from the memory module. | 05-29-2014 |
20140245105 | SEMICONDUCTOR MEMORY DEVICES INCLUDING ERROR CORRECTION CIRCUITS AND METHODS OF OPERATING THE SEMICONDUCTOR MEMORY DEVICES - A memory controller includes a controller input/output circuit configured to output a first command to read first data, and output a second command to read an error corrected portion of the first data. A memory device includes: an error detector, a data storage circuit and an error correction circuit. The error detector is configured to detect a number of error bits in data read from a memory cell in response to a first command. The data storage circuit is configured to store the read data if the detected number of error bits is greater than or equal to a first threshold value. The error correction circuit is configured to correct the stored data. | 08-28-2014 |
20140268978 | SEMICONDUCTOR MEMORY DEVICE HAVING ASYMMETRIC ACCESS TIME - A semiconductor memory device may include a plurality of data input/output DQ pads and a plurality of first and second memory cell arrays. Each path of a first set of data paths from each of the plurality of first memory cell arrays to a corresponding DQ pad is physically shorter than each path of a second set of data paths from each of the plurality of second memory cell arrays to the corresponding DQ pad. Each of the plurality of first memory cell arrays is a designated first-speed access cell array and each of the plurality of second memory cell arrays is a designated second-speed access cell array, the second-speed being slower than the first-speed. A size of the each of the plurality of first memory cell arrays is smaller than a size of the each of the plurality of second memory cell arrays. | 09-18-2014 |
20140310481 | MEMORY SYSTEM - A memory system includes a memory controller to control a first memory device and a second memory device. The first and second memory devices are different in terms of at least one of physical distance from the memory controller, a manner of connection to the memory controller, error correction capability, or memory supply voltage. The first and second memory devices also have different latencies. | 10-16-2014 |
20140317469 | MEMORY DEVICE FOR PERFORMING ERROR CORRECTION CODE OPERATION AND REDUNDANCY REPAIR OPERATION - Provided are a memory device and a memory module, which perform both an ECC operation and a redundancy repair operation. The memory device repairs a single-bit error due to a ‘fail’ cell by using an error correction code (ECC) operation, and also repairs the ‘fail’ cell by using a redundancy repair operation when the ‘fail’ cell is not repairable by the ECC operation. The redundancy repair operation includes a data line repair and a block repair. The ECC operation may change a codeword corresponding to data per one unit of memory cells including the ‘fail’ cell, and may also change the size of parity bits regarding the changed codeword. | 10-23-2014 |
20140355332 | VOLATILE MEMORY DEVICE AND REFRESH METHOD THEREOF - Provided is a refresh method of a volatile memory device. The method includes: detecting a number of disturbances that affect a second memory area as the number of accesses to a first memory area is increased; outputting an alert signal from the volatile memory device to an outside of the volatile memory device when the detected number of disturbances reach a reference value; and performing a refresh operation on the second memory area in response to the alert signal. | 12-04-2014 |
20150049570 | MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME, OPERATING METHOD THEREOF - In one embodiment, the memory device includes at least one memory bank including first and second subbanks, and control logic configured to control storing data into the memory bank. The control logic is configured to activate the first subbank and to precharge the second subbank in response to a first activate command for the first subbank. | 02-19-2015 |
20150089327 | SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME - The semiconductor memory device includes a memory cell array and an error correction code (ECC) circuit. The memory cell array is divided into a first memory region and a second memory region. Each of the first and second memory regions includes a plurality of pages each page including a plurality of memory cells connected to a word line. The ECC circuit corrects single-bit errors of the first memory region using parity bits. The first memory region provides a consecutive address space to an external device by correcting the single-bit errors using the ECC circuit and the second memory region is reserved for repairing at least one of a first failed page of the first memory region or a second failed page of the second memory region. | 03-26-2015 |