| Patent application number | Description | Published |
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| 20080245870 | METHOD FOR PROVIDING MOBILE SERVICE USING CODE-PATTERN - A method and apparatus for providing a mobile service with the use of a code pattern is disclosed In one embodiment, the method comprising: taking a photograph of a code pattern image, decoding the photographed code pattern image so as to obtain code information, extracting uniform resourse locator (URL) information corresponding to the code information, transmitting a content information request message to a service provider server corresponding to the URL information, and receiving content information corresponding to the URL information from the service provider server. According to embodiments of the present invention, it is possible to provide various and convenient mobile services to mobile terminal users using a mobile terminal, having a camera, and a code pattern containing the URL information. | 10-09-2008 |
| 20080247363 | METHOD FOR PROVIDING MOBILE SERVICE USING CODE-PATTERN - A method and apparatus for providing a mobile service with the use of a code pattern is disclosed In one embodiment, the method comprising: taking a photograph of a code pattern image, decoding the photographed code pattern image so as to obtain code information, extracting uniform resource locator (URL) information corresponding to the code information, transmitting a content information request message to a service provider server corresponding to the URL information, and receiving content information corresponding to the URL information from the service provider server. According to embodiments of the present invention, it is possible to provide various and convenient mobile services to mobile terminal users using a mobile terminal, having a camera, and a code pattern containing the URL information. | 10-09-2008 |
| 20090065566 | APPARATUS AND METHOD FOR PROVIDING CONTENTS BY USING MACHINE-READABLE CODE - According to the present invention, an apparatus and method for proving a user with a content by using a machine-readable code is provided. In one aspect of the present invention, provided is a method for implementation on a terminal for providing a user with at least one content by using a machine-readable code, the method comprising the steps of: receiving a machine-readable code; extracting a code value of the received machine-readable code; transferring the extracted code value to a first external computational device; receiving from the first external computational device at least one category associated with the extracted code value; transmitting the at least one category to a second external computational device; and receiving from the second external computational device at least one content belonging to the at least one category. | 03-12-2009 |
| 20090065567 | APPARATUS AND METHOD FOR PROVIDING CONTENTS BY USING MACHINE-READABLE CODE - According to the present invention, an apparatus and method for proving a user with a content by using a machine-readable code is provided. In an aspect of the present invention, provided is a method for implementation on a terminal for providing a user with at least one content by using a machine-readable code, the method comprising the steps of: receiving a machine-readable code; extracting a code value of the received machine-readable code; transferring the extracted code value to a first external computational device; receiving from the first external computational device at least one of a plurality of content IDs associated with the extracted code value; transmitting the at least one content ID to a second external computational device; and receiving from the second external computational device at least one content corresponding to the at least one content ID. | 03-12-2009 |
| 20090066386 | MTCMOS FLIP-FLOP WITH RETENTION FUNCTION - There is provided a MTCMOS flip-flop configured to operate at high speed and to reduce leakage current while realizing a retention function in a sleep mode. The MTCMOS flip-flop may include a signal generator adapted to output an internal clock signal or a sleep mode control signal based on changes in a retention signal and an external clock signal, a master latch adapted to latch an input signal and to output a master latch output signal based on the internal clock signal, and a slave latch connected to an actual ground and adapted to latch the master latch signal, to output a slave latch output signal under control of the internal clock signal, and to maintain the latched signal under control of the sleep mode control signal in the sleep mode. | 03-12-2009 |
| 20090257315 | POSITION TRACING SIGNAL GENERATOR UNIT AND INPUT SYSTEM HAVING THE SAME - Disclosed are a position tracing signal generator unit and an input system using the same. The position tracing signal generator unit of the present invention generates ultrasonic signals with a constant time interval to allow ultrasonic signals generated from a plurality of ultrasonic signal generator to be overlapped and amplified. It is possible to increase the intensity of the ultrasonic signal and lengthen the range. Due to the structural advantages of the present invention as described above, it is possible to solve a problem of the prior art, i.e., a large thickness of the position tracing signal generator unit caused by a large size of the ultrasonic sensor for increasing the intensity of the ultrasonic signal. | 10-15-2009 |
| 20090257452 | METHOD AND APPARATUS FOR PROVIDING AND RECEIVING THREE-DIMENSIONAL DIGITAL CONTENTS - Provided are a method and an apparatus for providing three-dimensional (3D) digital content by using a conventional system for providing two-dimensional (2D) digital content. The method includes generating an elementary stream (ES) regarding first data of 2D digital content, generating an ES regarding second data of 3D digital content, packetizing the ESs of the first data and the second data, and recording) the packetized second data and content information of the second data within header information of multiplexed stream of the packetized first data. | 10-15-2009 |
| Patent application number | Description | Published |
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| 20080219065 | DELAY LOCKED LOOP CIRCUIT FOR A SYNCHRONOUS SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF GENERATING INFORMATION ABOUT A LOAD CONNECTED TO A DATA PIN OF A SYNCHRONOUS SEMICONDUCTOR MEMORY DEVICE - A delay locked loop (DLL) circuit for a synchronous semiconductor memory device which can control a delay time of a feedback loop within the DLL circuit according to the magnitude of an external load, and a method of generating information about a load connected to a data pin of a synchronous semiconductor memory device are provided. The DLL circuit includes a replica output driver delaying an internal clock signal by a first delay time to output a first internal clock signal, the first delay time is a delay time of the internal clock signal which is generated by an output driver when a first load of a first magnitude is connected to an output terminal of the output driver, and a transfer/delay circuit transferring the first delay internal clock signal to a phase detector as a second delay internal clock signal when the first load is connected to the output terminal, and outputting the second delay internal clock signal to the phase detector by delaying the first delay internal clock signal by a second delay time, the second delay time is a delay time of the internal clock signal which is generated by the output driver when a second load of a second magnitude, which is larger than the first magnitude, is connected to the output terminal. | 09-11-2008 |
| 20080247212 | MEMORY SYSTEM HAVING POINT-TO-POINT (PTP) AND POINT-TO-TWO-POINT (PTTP) LINKS BETWEEN DEVICES - A memory system has first and second primary memories and first and second secondary memories coupled to the first and second primary memories, respectively, the coupling comprising at least one point-to-point connection. A memory module includes at least two of the first and second primary and first and second secondary memories. A first connection element, such as a connector or solder, connects the memory module to a mother board. A second connection element, such as a connector or solder, connects at least one other of the first and second primary and first and second secondary memories to the mother board. At least one of the memories on the first memory module is coupled to at least one of the other memories. The memory system also includes a memory controller which is connected to the primary memories by a point-to-two-point link. | 10-09-2008 |
| 20090080272 | DELAY LOCKED LOOP CIRCUIT FOR A SYNCHRONOUS SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF GENERATING INFORMATION ABOUT A LOAD CONNECTED TO A DATA PIN OF A SYNCHRONOUS SEMICONDUCTOR MEMORY DEVICE - A delay locked loop (DLL) circuit for a synchronous semiconductor memory device which can control a delay time of a feedback loop within the DLL circuit according to the magnitude of an external load, and a method of generating information about a load connected to a data pin of a synchronous semiconductor memory device are provided. The DLL circuit includes a replica output driver delaying an internal clock signal by a first delay time to output a first internal clock signal, the first delay time is a delay time of the internal clock signal which is generated by an output driver when a first load of a first magnitude is connected to an output terminal of the output driver, and a transfer/delay circuit transferring the first delay internal clock signal to a phase detector as a second delay internal clock signal when the first load is connected to the output terminal, and outputting the second delay internal clock signal to the phase detector by delaying the first delay internal clock signal by a second delay time, the second delay time is a delay time of the internal clock signal which is generated by the output driver when a second load of a second magnitude, which is larger than the first magnitude, is connected to the output terminal. | 03-26-2009 |
