| Patent application number | Description | Published |
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| 20080278992 | INDEPENDENT-GATE CONTROLLED ASYMMETRICAL MEMORY CELL AND MEMORY USING THE CELL - Techniques are provided for employing independent gate control in asymmetrical memory cells. A memory circuit, such as an SRAM circuit, can include a number of bit line structures, a number of word line structures that intersect the bit line structures to form a number of cell locations, and a number of asymmetrical memory cells located at the cell locations. Each of the asymmetrical cells can be selectively coupled to a corresponding one of the bit line structures under control of a corresponding one of the word line structures. Each of the cells can include a number of field effect transistors (FETS), and at least one of the FETS can be configured with separately biased front and back gates. One gate can be biased separately from the other gate in a predetermined manner to enhance read stability of the asymmetrical cell. | 11-13-2008 |
| 20080315907 | Methods of Operating an Electronic Circuit for Measurement of Transistor Variability and the Like - An electronic circuit includes an output terminal and at least a first measuring FET. The second drain-source terminals of a plurality of FETS to be tested are interconnected with the first drain-source terminal of the first measuring FET and the output terminal. The second drain-source terminal of the first measuring FET is interconnected with a first biasing terminal. The first drain-source terminals of the FETS to be tested are interconnected with a second biasing terminal. A state machine is coupled to the gates of the FETS to be tested and the gate of the first measuring FET. The state machine is configured to energize the gate of the first measuring FET and to sequentially energize the gates of the FETS to be tested, so that an output voltage appears on the output terminal. Circuitry to compare the output voltage to a reference value is also provided. The gate of the first measuring field effect transistor is energized; the gates of the field effect transistors to be tested are sequentially energized, whereby an output voltage appears on the output terminal; and the output voltage is compared to the reference value. | 12-25-2008 |
| 20090067223 | COMPUTER-READABLE MEDIUM ENCODING A BACK-GATE CONTROLLED ASYMMETRICAL MEMORY CELL AND MEMORY USING THE CELL - Techniques are provided for back-gate control in an asymmetrical memory cell. In one aspect, the cell includes five transistors and can be employed for static random access memory (SRAM) applications. An inventive memory circuit can include a plurality of bit line structures, a plurality of word line structures that intersect the plurality of bit line structures to form a plurality of cell locations, and a plurality of cells located at the plurality of cell locations. Each cell can be selectively coupled to a corresponding one of the bit line structures under control of a corresponding one of the word line structures. Each cell can include a first inverter having first and second field effect transistors (FETS) and a second inverter with third and fourth FETS that is cross-coupled to the first inverter to form a storage flip-flop. One of the FETS in the first inverter can be configured with independent front and back gates and can function as both an access transistor and part of one of the inverters. | 03-12-2009 |
| 20090147592 | Memory Circuit with Decoupled Read and Write Bit Lines and Improved Write Stability - In a memory circuit, data from all cells along a selected word line is read. Then, the read data is written back to half-selected cells and new data is written to the selected cells in the next cycle. In cases where a READ bit line (RBL) and WRITE bit line (WBL) are decoupled, RBL and WBL can be accessed simultaneously. Hence, the WRITE in the n-th cycle can be delayed to the n+1-th cycle as far as there is no data hazard such as reading data from memory before correct data are actually written to memory. As a result, there is no bandwidth loss, although the latency of the WRITE operation increases. WRITE stability issues in previous configurations with decoupled RBL and WBL are thus addressed. | 06-11-2009 |
| 20090309625 | ELECTRONIC CIRCUIT FOR MEASUREMENT OF TRANSISTOR VARIABILITY AND THE LIKE - An electronic circuit includes an output terminal and at least a first measuring FET. The second drain-source terminals of a plurality of FETS to be tested are interconnected with the first drain-source terminal of the first measuring FET and the output terminal. The second drain-source terminal of the first measuring FET is interconnected with a first biasing terminal. The first drain-source terminals of the FETS to be tested are interconnected with a second biasing terminal. A state machine is coupled to the gates of the FETS to be tested and the gate of the first measuring FET. The state machine is configured to energize the gate of the first measuring FET and to sequentially energize the gates of the FETS to be tested, so that an output voltage appears on the output terminal. Circuitry to compare the output voltage to a reference value is also provided. The gate of the first measuring field effect transistor is energized; the gates of the field effect transistors to be tested are sequentially energized, whereby an output voltage appears on the output terminal; and the output voltage is compared to the reference value. | 12-17-2009 |
| Patent application number | Description | Published |
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| 20090018787 | APPARATUS AND METHOD FOR DETERMINING THE SLEW RATE OF A SIGNAL PRODUCED BY AN INTEGRATED CIRCUIT - Determining a slew rate of a signal from an integrated circuit under test by comparing the signal with a first reference voltage, comparing the signal with a second reference voltage different from the first reference voltage, generating an output pulse having a pulse width indicative of a slew rate of the signal, and integrating the output pulse over time to generate an output voltage proportional to the pulse width; wherein the output voltage is indicative of the slew rate of the signal produced by the integrated circuit. | 01-15-2009 |
| 20090091346 | CIRCUITS AND METHODS FOR CHARACTERIZING DEVICE VARIATION IN ELECTRONIC MEMORY CIRCUITS - A circuit includes a comparator circuit configured such that its output toggles from a first digital logical level to a second digital logical level when its first and second inputs transition between a first state wherein the first input has an applied voltage greater than an applied voltage at the second input and a second state wherein the first input has an applied voltage less than an applied voltage at the second input. A plurality of cells each have at least one series-connected pair of field effect transistors interconnected at an output node intermediate the field effect transistors. Decoding logic is configured to select a given one of the cells for measurement, and selectively interconnect the output node of the given one of the cells to the first input of the comparator circuit. Voltage supply circuitry is configured to (i) apply voltages to the gates of the pair of transistors of the given one of the cells selected for measurement, such that the pair of transistors operate in a linear region, and have a variable voltage difference, Δ, between their gate-to-source voltages, and (ii) vary the Δ until the comparator circuit output toggles from the first digital logical level to the second digital logical level. | 04-09-2009 |
| 20090185409 | ENHANCED STATIC RANDOM ACCESS MEMORY STABILITY USING ASYMMETRIC ACCESS TRANSISTORS AND DESIGN STRUCTURE FOR SAME - A memory circuit includes a plurality of bit line structures (each including a true and a complementary bit line), a plurality of word line structures intersecting the plurality of bit line structures to form a plurality of cell locations and a plurality of cells located at the plurality of cell locations. Each of the cells includes a logical storage element, a first access transistor selectively coupling a given one of the true bit lines to the logical storage element, and a second access transistor selectively coupling a corresponding given one of the complementary bit lines to the logical storage element. One or both of the first and second access transistors are configured with asymmetric current characteristics to enable independent enhancement of READ and WRITE margins. Also included within the | 07-23-2009 |
| 20090189703 | CIRCUITS AND DESIGN STRUCTURES FOR MONITORING NBTI (NEGATIVE BIAS TEMPERATURE INSTABILITY) EFFECT AND/OR PBTI (POSITIVE BIAS TEMPERATURE INSTABILITY) EFFECT - A ring oscillator has an odd number of NOR-gates greater than or equal to three, each with first and second input terminals, a voltage supply terminal, and an output terminal. The first input terminals of all the NOR-gates are interconnected, and each of the NOR-gates has its output terminal connected to the second input terminal of an immediately adjacent one of the NOR-gates. During a stress mode, a voltage supply and control block applies a stress enable signal to the interconnected first input terminals, and an increased supply voltage to the voltage supply terminals. During a measurement mode, this block grounds the interconnected first input terminals, and applies a normal supply voltage to the voltage supply terminals. Also included are an analogous NAND-gate based circuit, a circuit combining the NAND- and NOR-aspects, a circuit with a ring oscillator where the inverters may be coupled directly or through inverting paths, and circuits for measuring the bias temperature instability effect in pass gates. | 07-30-2009 |
| 20090190426 | CIRCUITS, METHODS AND DESIGN STRUCTURES FOR ADAPTIVE REPAIR OF SRAM ARRAYS - The circuit includes a static random access memory array having a plurality of cells, in turn having a plurality of devices; as well as a global sensor having at least one output, coupled to the static random access memory array, and configured to sense at least one of global readability and global write-ability. Also included is a decision-making circuit coupled to the at least one output of the global sensor. The decision-making circuit is configured to determine, from the at least one output of the global sensor, whether adaptation signals are required to correct global readability and/or write-ability. An adaptation signal generation block is also included and is coupled to the decision-making circuit and the array, and configured to supply the adaptation signals to the array, responsive to the decision-making circuit determining that the adaptation signals are required. At least the array and the global sensor, and preferably the decision-making circuit and the adaptation signal generation block as well, are implemented on a single integrated circuit chip. An associated method and design structure(s) are also provided. | 07-30-2009 |
| 20090251974 | MEMORY CIRCUITS WITH REDUCED LEAKAGE POWER AND DESIGN STRUCTURES FOR SAME - A memory circuit includes a global read bit line, a global read bit line latch, and a plurality of sub-arrays, each of which includes first and second local read bit lines, first and second local write bit lines, and first and second pluralities of memory cells interconnected, respectively, with the first and second local read bit lines and the first and second local write bit lines. The local read bit lines are decoupled from the local write bit lines. A local multiplexing block is interconnected with the first and second local read bit lines and is configured to ground the first and second local read bit lines upon assertion of a SLEEP signal, and to selectively interconnect the local read bit lines to the global read bit line. A global multiplexing block is interconnected with the global read bit line and is configured to maintain the global read bit line in a substantially discharged state upon assertion of the SLEEP signal and to interconnect the global read bit line to the global read bit line latch. Also included are design structures for circuits of the kind described. | 10-08-2009 |
| 20090310430 | METHODS FOR CHARACTERIZING DEVICE VARIATION IN ELECTRONIC MEMORY CIRCUITS - A circuit includes a comparator circuit configured such that its output toggles from a first digital logical level to a second digital logical level when its first and second inputs transition between a first state wherein the first input has an applied voltage greater than an applied voltage at the second input and a second state wherein the first input has an applied voltage less than an applied voltage at the second input. A plurality of cells each have at least one series-connected pair of field effect transistors interconnected at an output node intermediate the field effect transistors. Decoding logic is configured to select a given one of the cells for measurement, and selectively interconnect the output node of the given one of the cells to the first input of the comparator circuit. Voltage supply circuitry is configured to (i) apply voltages to the gates of the pair of transistors of the given one of the cells selected for measurement, such that the pair of transistors operate in a linear region, and have a variable voltage difference, Δ, between their gate-to-source voltages, and (ii) vary the Δ until the comparator circuit output toggles from the first digital logical level to the second digital logical level. | 12-17-2009 |
