Patent application number | Description | Published |
20080218292 | Low voltage data transmitting circuit and associated methods - A low voltage data transmitting circuit (LVDTC) may be connected to a first transmission line that transmits a first voltage signal to a receiver and a second transmission line that transmits a second voltage signal to the receiver. The LVDTC includes a first resistor coupled to the first transmission line, a second resistor coupled to the second transmission line, and a control unit coupled to the first transmission line and the second transmission line, the control unit being configured to control voltage levels of the first and second voltage signals such that the voltage levels of the first and second voltage signals are higher than a ground voltage level of the receiver, wherein the first and second voltage signals may constitute a differential pair. | 09-11-2008 |
20090015537 | DISPLAY DEVICE TRANSFERRING DATA SIGNAL WITH CLOCK - A display device includes; a panel, a timing controller generating an embedded clock data signal combining image data and a clock signal, and a column driver driving the panel in response to the embedded clock data signal. The data bits within the embedded clock data signal are communicated at one of three voltage levels in a three-level signaling scheme, and the timing controller determines one of the three voltage levels for a current data bit (DIN[n]) within the embedded clock data signal in relation to a voltage level of a previous data bit (DIN[n−1]) within the embedded clock data signal. | 01-15-2009 |
20100244914 | CLOCK GENERATOR TO REDUCE LONG TERM JITTER - A clock generator includes a controller, a digital phase locked loop (PLL) circuit, a charge pump phase locked loop (PLL) circuit and a divider. The controller generates a division factor and a first internal clock signal in response to a low-frequency reference clock signal and a multiplication factor. The digital PLL circuit generates a second internal clock signal in response to the reference clock signal, the division factor and the first internal clock signal. The charge pump PLL circuit generates a plurality of third internal clock signals by using the second internal clock signal. The divider generates a high-frequency clock signal in response to a phase selection signal, the division factor and the third internal clock signals. | 09-30-2010 |
20110227616 | PHASE LOCKED LOOP CIRCUIT, METHOD OF DETECTING LOCK, AND SYSTEM HAVING THE CIRCUIT - Provided are a phase locked loop (PLL) circuit, a lock detector employable with a PLL circuit, a system including such a PLL circuit and/or lock detector, and a method of detecting a lock/unlock state of a PLL circuit. The PLL circuit may include a clock generating circuit configured to generate an output clock signal having a predetermined frequency in synchronization with a reference clock signal. The lock detector may be configured to determine that the PLL circuit is in a lock state when a phase difference between the reference clock signal and the output clock signal is equal to or less than a first reference value, determine that the PLL circuit is in an unlock state when the phase difference between the reference clock signal and the output clock signal is greater than a second reference value, and generate a lock detection signal. | 09-22-2011 |
20110227617 | PHASE LOCKED LOOP CIRCUIT AND SYSTEM HAVING THE SAME - A phase locked loop (PLL) circuit and a system including such a PLL that may at least compensate for leakage current in a loop filter. The PLL circuit may include a voltage adjusting unit configured to pump charges based on a phase difference between an oscillation clock signal and a reference clock signal, a loop filter configured to generate a frequency control voltage, a level of which is shifted by the charge pumping of the voltage adjusting unit, a voltage controlled oscillator (VCO) configured to output the oscillation clock signal having a frequency corresponding to the frequency control voltage, and a current control circuit configured to generate a compensation current corresponding to a leakage current generated by the loop filter and allow the compensation current and the leakage current to substantially and/or completely counterbalance each other. | 09-22-2011 |
20120183104 | DIGITAL PHASE FREQUENCY DETECTOR, DIGITAL PHASE LOCKED LOOP INCLUDING THE SAME AND METHOD OF DETECTING PHASE AND FREQUENCY OF OUTPUT SIGNAL - A digital phase frequency detector includes a detection unit, a reset unit and a phase comparison unit. The detection unit detects edges of a reference signal and a feedback input signal to generate a reference edge signal and a feedback edge signal. The reset unit generates a reset signal resetting the detection unit based upon the reference edge signal and the feedback edge signal. The phase comparison unit generates first and second phase comparison signals based upon the reference edge signal and the feedback edge signal. The phase comparison unit includes a first flip-flop generating a first comparison signal based upon the reference edge signal and the feedback edge signal, a second flip-flop generating a second comparison signal based upon the reference edge signal and the feedback edge signal, and a latch block latching the first and second comparison signals to generate the first and second phase comparison signals. | 07-19-2012 |
20120319765 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF SUPPLYING POWER TO THE SAME - A semiconductor IC including a supply voltage generator, one or more first circuit blocks, and one or more second circuit blocks. The supply voltage generator is configured to generate a first supply voltage and a second supply voltage based on an external supply voltage, and to provide the first supply voltage to a first power bus and the second supply voltage to a second power bus. The first circuit blocks are connected between the first power bus and the second power bus, and the second circuit blocks are connected between the second power bus and ground. | 12-20-2012 |
20130187685 | DITHER CONTROL CIRCUIT AND DEVICES HAVING THE SAME - A dither control circuit includes a pseudo random number generator, which generates a pseudo random number sequence in response to a frequency-divided clock signal, and a dither circuit which dithers an input digital code by using at least one output bit of the pseudo random number sequence and outputs a dithered digital code corresponding to a result of the dithering. The dither circuit may output, as the dithered digital code, a digital code corresponding to a sum of or a difference between the input digital code and the input digital code based on the at least one output bit. The dithered digital code may be input to an accumulator which operates in-sync with the frequency-divided clock signal. | 07-25-2013 |
20140203879 | TEMPERATURE CONTROLLED OSCILLATOR AND TEMPERATURE SENSOR INCLUDING THE SAME - A temperature controlled oscillator includes an oscillation unit and a filter unit. The oscillation unit is configured to generate at least one reference voltage based on a supply voltage and a ground voltage, and to generate an oscillation signal having a period varying according to a temperature, the oscillation unit configured to generate the oscillation signal based on a filter voltage and the at least one reference voltage. The filter unit is configured to generate the filter voltage based on the oscillation signal. | 07-24-2014 |
20140232477 | SEALED CRYSTAL OSCILLATOR AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME - A semiconductor package includes a package substrate; an integrated circuit chip formed on one surface of the package substrate; and a sealed quartz oscillator formed on at least one of an inside, one surface, and the other surface of the package substrate, wherein the sealed quartz oscillator includes a substrate, a quartz blank formed on one surface of the substrate, and a sealing cap covering at least one surface of the quartz blank and including metal. | 08-21-2014 |
20140266137 | CURRENT GENERATOR, METHOD OF OPERATING THE SAME, AND ELECTRONIC SYSTEM INCLUDING THE SAME - A current generator includes a first current generation circuit configured to generate a first current having a first current noise which depends on a change in a supply voltage, a second current generation circuit configured to generate a second current having a second current noise which depends on the change in the supply voltage, and a current subtracting circuit configured to generate a third current with the first current noise and the second current noise removed by subtracting the second current from the first current. | 09-18-2014 |
20140266341 | DIGITAL PHASE-LOCKED LOOP USING PHASE-TO-DIGITAL CONVERTER, METHOD OF OPERATING THE SAME, AND DEVICES INCLUDING THE SAME - A digital phase locked loop (DPLL), a method of operating the same, and a device including the same are provided. The DPLL includes a digitally-controlled oscillator configured to change a frequency and a phase of an output oscillation signal in response to a digital control code; a main divider configured to divide the frequency of the output oscillation signal and generate a first feedback signal based on the divided frequency; and a phase-to-digital converter configured to subdivide the phase of the output oscillation signal and to generate a quantized code by converting a phase difference between a reference signal and the first feedback signal using a phase-subdivided signal resulting from the subdivision. The digital control code is generated based on the quantized code. | 09-18-2014 |
20140266346 | ALL-DIGITAL PHASE-LOCKED LOOP FOR ADAPTIVELY CONTROLLING CLOSED-LOOP BANDWIDTH, METHOD OF OPERATING THE SAME, AND DEVICES INCLUDING THE SAME - A method of operating an all-digital phase-locked loop (ADPLL) includes detecting a phase change in a feedback signal of the ADPLL using a search window and controlling a closed-loop bandwidth of the ADPLL based on a detection result. The closed-loop bandwidth when the phase change is detected outside the search window is greater than the closed-loop bandwidth when the phase change is detected within the search window. | 09-18-2014 |
20140266371 | MULTI-PHASE GENERATOR - A multi-phase generator includes an oscillator unit including a plurality of first buffer units forming a single closed loop and a delay unit including a plurality of second buffer units respectively connected to a plurality of nodes, wherein each of the plurality of nodes is connected between two adjacent buffer units of the first buffer units. A phase of an output signal of a second buffer unit, among the second buffer units, lags behind a phase of an output signal of a first buffer unit, among the first buffer units. | 09-18-2014 |