| Patent application number | Description | Published |
|---|
| 20090242866 | Phase change memory device and method of fabricating the same - A semiconductor device includes an insulating layer on a substrate, a first electrode in the insulating layer having a first upper surface and a second upper surface, a second electrode in the insulating layer spaced apart from the first electrode by a first distance and having a third upper surface and a fourth upper surface, the third upper surface being disposed at a substantially same level as the first upper surface, and the fourth upper surface being disposed at a substantially same level as the second upper surface, a first phase change material pattern covering a part of the first upper surface of the first electrode, and a second phase change material pattern covering a part of the third upper surface of the second electrode, wherein an interface region between the second phase change pattern and the second electrode is spaced apart from an interface region between the first phase change pattern and the first electrode by a second distance greater than the first distance. | 10-01-2009 |
| 20100038624 | MEMORY DEVICE HAVING HIGHLY INTEGRATED CELL STRUCTURE AND METHOD OF ITS FABRICATION - In an embodiment, a memory device, with a highly integrated cell structure, includes a mold insulating layer disposed on a semiconductor substrate. At least one conductive line is disposed on the mold insulating layer. Data storage elements self-aligned with the conductive line are interposed between the conductive line and the mold insulating layer. In this case, each of the data storage elements may include a resistor pattern and a barrier pattern, which are sequentially stacked, and the resistor pattern may be self-aligned with the barrier pattern. | 02-18-2010 |
| 20100051952 | THIN FILM TRANSISTOR SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A thin film transistor substrate capable of appropriately maintaining driving performance even when there is a difference between manufacturing processes and a method of manufacturing the same. The thin film transistor substrate includes: a gate electrode formed on an insulating substrate; a semiconductor layer formed on the gate electrode; and a plurality of thin film transistors each having a source electrode and a drain electrode that are formed on the gate electrode and the semiconductor layer so as to be spaced apart from each other. At least one of the plurality of thin film transistors is a dummy thin film transistor that does not have the semiconductor layer between the source electrode and the drain electrode. | 03-04-2010 |
| 20100090194 | MULTI-BIT PHASE-CHANGE RANDOM ACCESS MEMORY (PRAM) WITH DIAMETER-CONTROLLED CONTACTS AND METHODS OF FABRICATING AND PROGRAMMING THE SAME - A phase-change random-access memory (PRAM) device includes a chalcogenide element, the chalcogenide element comprising a material which can assume a crystalline state or an amorphous state upon application of a heating current. A first contact is connected to a first region of the chalcogenide element and has a first cross-sectional area. A second contact is connected to a second region of the chalcogenide element and having a second cross-sectional area. A first programmable volume of the chalcogenide material is defined in the first region of the chalcogenide element, a state of the first programmable volume being programmable according to a resistance associated with the first contact. A second programmable volume of the chalcogenide material is defined in the second region of the chalcogenide element, a state of the second programmable volume being programmable according to a second resistance associated with the second contact. | 04-15-2010 |
| 20100159638 | Method of fabricating nonvolatile memory device - A method of manufacturing a nonvolatile memory device including forming on a lower insulating layer a first sacrificial pattern having first openings extending in a first direction, forming a second sacrificial pattern having second openings extending in a second direction on the lower insulating layer and the first sacrificial pattern wherein the second openings intersect the first openings, etching the lower insulating layer using the first and second sacrificial patterns to form a lower insulating pattern having contact holes defined by a region where the first and second openings intersect each other, forming a bottom electrode in the contact holes, and forming a variable resistance pattern on the lower insulating pattern so that a portion of the variable resistance pattern connects to a top surface of the bottom electrode. | 06-24-2010 |
| 20100159675 | METHOD FABRICATING NONVOLATILE MEMORY DEVICE - A method of fabricating a nonvolatile memory device includes; forming a first sacrificial layer pattern including a first open area that extends in a first direction on a lower dielectric layer, forming a pre-lower dielectric layer pattern including a recess that extends in the first direction using the first sacrificial layer pattern, forming a second sacrificial layer pattern including a second open area that extends in a second direction on the pre-lower dielectric layer pattern and the first sacrificial layer pattern, wherein the second open area intersects the first open area, forming a lower dielectric layer pattern including contact holes spaced apart in the recess using the first sacrificial layer pattern and second sacrificial layer pattern, wherein the contact holes extend to a bottom of the lower dielectric layer pattern, and forming a bottom electrode in the contact hole. | 06-24-2010 |
| 20100171090 | Semiconductor phase-change memory device - A semiconductor phase-change memory device comprises a data line disposed on a semiconductor substrate and a data storage structure disposed under the data line and having a concave portion extending in a direction along the data line. A data contact structure is configured to contact the data storage structure, and having a lower portion filling the concave portion of the data storage structure and an upper portion surrounding at least a lower portion of the data line. Each of sidewalls of the data storage structure is disposed at substantially the same plane as a corresponding one of sidewalls of the upper portion of the data contact structure. | 07-08-2010 |
| 20100225870 | ARRAY SUBSTRATE, METHOD OF MANUFACTURING THE SAME AND METHOD OF REPAIRING THE SAME - An array substrate includes a substrate including a display area and a peripheral area surrounding the display area, data lines disposed in the display area and including a portion thereof extending from the display area into the peripheral area at a first side of a periphery of the display area, and a repair line disposed in the peripheral area and crossing the portion of the data lines extending into the peripheral area. The array substrate also includes a static electricity diode part electrically connected to the repair line and a first data line of the data lines. | 09-09-2010 |
