| Patent application number | Description | Published |
|---|
| 20080273377 | METHODS OF WRITING DATA TO MAGNETIC RANDOM ACCESS MEMORY DEVICES WITH BIT LINE AND/OR DIGIT LINE MAGNETIC LAYERS - A magnetic random access memory (MRAM) device may include a substrate, a first magnetic layer on the substrate, and a digit line on the first magnetic layer. A magnetic tunnel junction structure may be provided adjacent the digit line, and a bit line may be provided on the magnetic tunnel junction structure such that the magnetic tunnel junction structure is between the bit line and the digit line. In addition, a second magnetic layer may be provided on the bit line. | 11-06-2008 |
| 20080280390 | METHOD OF FABRICATING SEMICONDUCTOR MEMORY DEVICE HAVING SELF-ALIGNED ELECTRODE, RELATED DEVICE AND ELECTRONIC SYSTEM HAVING THE SAME - A method of fabricating a semiconductor memory device having a self-aligned electrode is provided. An interlayer insulating layer having a contact hole is formed on a substrate. A phase change pattern partially filling the contact hole is formed. A bit line which includes a bit extension self-aligned to the phase change pattern and crosses over the interlayer insulating layer is formed. The bit extension may extend in the contact hole on the phase change pattern. The bit extension contacts the phase change pattern. | 11-13-2008 |
| 20090026439 | Phase Change Memory Cells Having a Cell Diode and a Bottom Electrode Self-Aligned with Each Other - Integrated circuit devices are provide having a vertical diode therein. The devices include an integrated circuit substrate and an insulating layer on the integrated circuit substrate. A contact hole penetrates the insulating layer. A vertical diode is in lower region of the contact hole and a bottom electrode in the contact hole has a bottom surface on a top surface of the vertical diode. The bottom electrode is self-aligned with the vertical diode. A top surface area of the bottom electrode is less than a horizontal section area of the contact hole. Methods of forming the integrated circuit devices and phase change memory cells are also provided. | 01-29-2009 |
| 20090166600 | INTEGRATED CIRCUIT DEVICES HAVING A STRESS BUFFER SPACER AND METHODS OF FABRICATING THE SAME - Integrated circuit devices include an integrated circuit substrate and an insulating layer on the integrated circuit substrate. A contact hole penetrates the insulating layer. A vertical diode is in the contact hole and a stress buffer spacer is provided between the vertical diode and the insulating layer. Methods of forming the integrated circuit devices are also provided. | 07-02-2009 |
| 20090268515 | Twin-Cell Semiconductor Memory Devices - Twin cell type semiconductor memory devices are provided that include a plurality of main bit lines and a plurality of reference bit lines. Each of the reference bit lines correspond to respective ones of the main bit lines to form a plurality of bit line pairs. A plurality of sense amplifiers are provided that are electrically connected to a respective one of the plurality of bit line pairs. At least one of the plurality of main bit lines or the plurality of reference bit lines is interposed between the main bit line and the corresponding reference bit line of each bit line pair. At least some of the main bit lines may cross respective ones of the reference bit lines in a sense amplifier region of the semiconductor memory device that contains the plurality of sense amplifiers. | 10-29-2009 |
| 20090302297 | PHASE CHANGE MEMORY DEVICES AND THEIR METHODS OF FABRICATION - In an embodiment, a phase change memory device includes a semiconductor substrate of a first conductivity type and a first interlayer insulating layer disposed on the semiconductor substrate. A hole penetrates the first interlayer insulating layer. A first and a second semiconductor pattern are sequentially stacked in a lower region of the hole. A cell electrode is provided on the second semiconductor pattern. The cell electrode has a lower surface than a top surface of the first interlayer insulating layer. A confined phase change material pattern fills the hole on the cell electrode. An upper electrode is disposed on the phase change material pattern. The phase change material pattern in the hole is self-aligned with the first and second semiconductor patterns by the hole. A method of fabricating the phase change memory device is also provided. | 12-10-2009 |
| 20100044667 | SEMICONDUCTOR DEVICES HAVING A PLANARIZED INSULATING LAYER - A semiconductor device includes at least one phase-change pattern disposed on a semiconductor substrate. A planarized capping layer, a planarized protecting layer, and a planarized insulating layer are sequentially stacked to surround sidewalls of the at least one phase-change pattern. An interconnection layer pattern is disposed on the planarized capping layer, the planarized protecting layer, and the planarized insulating layer. The interconnection layer pattern is in contact with the phase-change pattern. | 02-25-2010 |
| 20100108971 | Methods of Forming Integrated Circuit Devices Having Vertical Semiconductor Interconnects and Diodes Therein and Devices Formed Thereby - Methods of forming integrated circuit devices include forming an etch stop layer on a surface of a semiconductor substrate and forming a first interlayer insulating layer on the etch stop layer. The first interlayer insulating layer is patterned to define an opening therein that exposes a first portion of the etch stop layer. This first portion of the etch stop layer is then removed to thereby expose an underlying portion of the surface of the semiconductor substrate. This removal of the etch stop layer may be performed by wet etching the first portion of the etch stop layer using a phosphoric acid solution. A semiconductor region is then selectively grown into the opening, using the exposed portion of the surface of the semiconductor substrate as an epitaxial seed layer. | 05-06-2010 |
| 20110115581 | APPARATUS AND METHOD FOR IMPLEMENTING LEFT-HANDED TRANSMISSION LINE - An apparatus for implementing a left-handed transmission line includes: a substrate coated with a conductor and having a rectangular shape with a predefined size; a plurality of concave-convex lines disposed on a bottom surface of the substrate; two conductive vias disposed on a top surface of the substrate; a first bonding wire connecting top portions of a conductive line between the concave-convex lines connected between the first etching surface and the second etching surface; and a second bonding wire connecting bottom portions of a conductive line between the concave-convex lines connected between the first etching surface and the second etching surface. | 05-19-2011 |
