| Patent application number | Description | Published |
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| 20090168580 | FUSE MONITORING CIRCUIT FOR SEMICONDUCTOR MEMORY DEVICE - A fuse monitoring circuit for a semiconductor device includes a repair fuse unit including a number of fuses to which a repair address is programmed, and configured to output fuse state signals corresponding to the connection states of the respective fuses in response to a fuse initialization signal. A serial fuse monitoring unit is configured to output a fuse state monitoring signal corresponding to each fuse state signal selected by an applied address in response to a serial monitoring test mode signal. Also, a parallel fuse monitoring unit is configured to output a repair monitoring signal by comparing an applied address and the repair address in response to a parallel monitoring test mode signal. An output unit is configured to output the fuse state monitoring signal and the repair monitoring signal to an output pad in response to an output control signal. | 07-02-2009 |
| 20090168581 | FUSE MONITORING CIRCUIT FOR SEMICONDUCTOR MEMORY DEVICE - A fuse monitoring circuit for a semiconductor memory device includes a fuse repair unit including a plurality of fuses each programmed with at least one repair address, configured to receive a fuse reset signal and to output a plurality of fuse state signals each corresponding to a connection state of one of the fuses, a fuse monitoring unit configured to receive a monitoring enable signal and to output a plurality of fuse state monitoring signals each corresponding to a corresponding one of the fuse state signals, each of the fuse state signals corresponding to one of a plurality of addresses, and an output unit configured to receive an output control signal and to output the fuse state monitoring signals to an output pad. | 07-02-2009 |
| 20090303650 | MONITORING CIRCUIT FOR SEMICONDUCTOR DEVICE - Provided is a technology for monitoring the electrical resistance of an element such as a fuse whose resistance is changed due to the electrical stress among internal circuits included in a semiconductor device. The present invention provides a monitoring circuit to monitor the change in the device specification during the device is being programmed and after the device is programmed. The present invention enables the verification of an optimized condition to let the device have a certain electrical resistance, by comparing the load voltage and the fuse voltage with the reference voltage that can sense the range of resistance variation more precisely. Also, it can guarantee device reliability since it is still possible to sense electrical resistance after the electrical stress is being given. Also, the present invention can increase the utility of the fuse by possessing an output to monitor electrical resistance sensed inside of the semiconductor. | 12-10-2009 |
| 20100109762 | INTERNAL VOLTAGE GENERATOR - An internal voltage generating circuit includes an internal voltage generating unit configured to generate an internal voltage that corresponds to a target voltage level by driving an internal voltage terminal with an external power supply voltage, and current sinking unit configured to adjust leakage current introduced to the internal voltage terminal in response to the external power supply voltage. | 05-06-2010 |
| 20100308901 | INTERNAL VOLTAGE GENERATING CIRCUIT - An internal voltage generating circuit is capable of controlling an amount of charge pumping according to an external power supply voltage. The internal voltage generating circuit includes a periodic signal generating unit configured to control generation of periodic signals according to a level of an external power supply voltage, and a pumping unit driven according to the periodic signals generated by the periodic signal generating unit. | 12-09-2010 |
| Patent application number | Description | Published |
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| 20080284486 | INTERNAL VOLTAGE GENERATOR OF SEMICONDUCTOR DEVICE AND METHOD FOR GENERATING INTERNAL VOLTAGE - An internal voltage generator of a semiconductor device consumes relatively small amount of driving current and generates a stable internal voltage with relatively small voltage level variation. The semiconductor device includes an oscillator configured to generate an oscillation signal in response to an input signal, wherein the oscillation signal oscillates with a first period and oscillates with a second period longer than the first period during a predetermined latter section, and an internal circuit configured to perform a predetermined operation in response to the oscillation signal. | 11-20-2008 |
| 20090167413 | SEMICONDUCTOR DEVICE AND DATA OUTPUTTING METHOD OF THE SAME - Semiconductor device and data outputting method of the same includes an on die thermal sensor (ODTS) configured to output temperature information by detecting an internal temperature of the semiconductor device and an output driver configured to control a slew rate depending on the temperature information and output data. | 07-02-2009 |
| 20100008161 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a charge pumping circuit, a level sensor, an oscillator, and a pumping control signal generator. The charge pumping circuit performs a negative-pumping operation to an external power in order to generate an internal voltage having a level lower than the external power. The level sensor senses a level of the internal voltage corresponding to a level of an adjusted reference voltage during a refresh mode. The oscillator generates a period signal in response to a sensing signal of the level sensor. The pumping control signal generator controls the operation of the charge pumping circuit in response to the period signal. | 01-14-2010 |
| 20100008173 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a charge pumping circuit, a level sensor, an oscillator, and a pumping control signal generator. The charge pumping circuit performs a negative-pumping operation to an external power in order to generate an internal voltage having a level lower than the external power. The level sensor senses a level of the internal voltage corresponding to a level of an adjusted reference voltage during a refresh mode. The oscillator generates a period signal in response to a sensing signal of the level sensor. The pumping control signal generator controls the operation of the charge pumping circuit in response to the period signal. | 01-14-2010 |
| 20100027364 | MULTI-PORT MEMORY DEVICE HAVING SELF-REFRESH MODE - The multi-port memory device includes a mode input/output controller for receiving a flag signal and generating a self-refresh entry signal and a self-refresh escape signal, a refresh interval signal generator for providing a self-refresh interval signal notifying a self-refresh interval in response to the self-refresh entry signal and the self-refresh escape signal, a refresh cycle signal generator for periodically generating a cycle-pulse signal during an activation of the self-refresh interval signal, an internal refresh signal generator for producing an internal refresh signal in response to the self-refresh entry signal and the cycle-pulse signal, and an internal address counter for generating an internal address in response to the internal refresh signal. | 02-04-2010 |
| 20100135057 | MULTI-PORT MEMORY DEVICE HAVING SERIAL INPUT/OUTPUT INTERFACE - A multi-port memory device includes a first package ball out region in which a plurality of balls for a serial I/O interface part are arranged; and a second package ball out region in which a plurality of balls for a dynamic random access memory (DRAM) part are arranged. | 06-03-2010 |
