| Patent application number | Description | Published |
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| 20100196592 | METHODS OF FABRICATING CAPACITORS INCLUDING LOW-TEMPERATURE CAPPING LAYERS - In a method of fabricating a capacitor, a lower electrode is formed, and a dielectric layer is formed on the lower electrode. An upper electrode is foamed on the dielectric layer opposite the lower electrode. A low-temperature capping layer is formed on the upper electrode at a temperature of less than about 300° C. Related devices and fabrication methods are also discussed. | 08-05-2010 |
| 20100200950 | Semiconductor device having dielectric layer with improved electrical characteristics and associated methods - A semiconductor device having a dielectric layer with improved electrical characteristics and associated methods, the semiconductor device including a lower metal layer, a dielectric layer, and an upper metal layer sequentially disposed on a semiconductor substrate and an insertion layer disposed between the dielectric layer and at least one of the lower metal layer and the upper metal layer, wherein the dielectric layer includes a metal oxide film and the insertion layer includes a metallic material film. | 08-12-2010 |
| 20100203725 | Methods of fabricating semiconductor devices and semiconductor devices including a contact plug processed by rapid thermal annealing - A method of fabricating a semiconductor device includes depositing tungsten on an insulating layer in which a contact hole is formed by chemical vapor deposition (CVD), performing chemical mechanical planarization (CMP) on the tungsten to expose the insulating layer and form a tungsten contact plug, and performing rapid thermal oxidation (RTO) on the tungsten contact plug in an oxygen atmosphere such that the tungsten expands volumetrically into tungsten oxide (W | 08-12-2010 |
| 20110045183 | METHODS OF FORMING A LAYER, METHODS OF FORMING A GATE STRUCTURE AND METHODS OF FORMING A CAPACITOR - In a method of forming a layer, a precursor including a metal and a ligand chelating to the metal is stabilized by contacting the precursor with an electron donating compound to provide a stabilized precursor onto a substrate. A reactant is introduced onto the substrate to bind to the metal in the stabilized precursor. The precursor stabilized by the electron donating compound has an improved thermal stability and thus the precursor is not dissociated at a high temperature atmosphere, and the layer having a uniform thickness is formed on the substrate. | 02-24-2011 |
| 20110073832 | PHASE-CHANGE MEMORY DEVICE - A phase-change memory device, including a lower electrode, a phase-change material pattern electrically connected to the lower electrode, and an upper electrode electrically connected to the phase-change material pattern. The lower electrode may include a first structure including a metal semiconductor compound, a second structure on the first structure, the second structure including a metal nitride material, and including a lower part having a greater width than an upper part, and a third structure including a metal nitride material containing an element X, the third structure being on the second structure, the element X including at least one selected from the group of silicon, boron, aluminum, oxygen, and carbon. | 03-31-2011 |
| 20110095397 | Semiconductor Structures Including Dielectric Layers and Capacitors Including Semiconductor Structures - Semiconductor structures including a first conductive layer; a dielectric layer on the first conductive layer; a second conductive layer on the dielectric layer; and a crystallized seed layer in at least one of a first portion between the first conductive layer and the dielectric layer and a second portion between the dielectric layer and the second conductive layer. Related capacitors and methods are also provided herein. | 04-28-2011 |
| 20110102968 | MULTILAYER STRUCTURE, CAPACITOR INCLUDING THE MULTILAYER STRUCTURE AND METHOD OF FORMING THE SAME - In a multilayer structure and a method of forming the same, a conductive layer including a metal nitride and a dielectric layer positioned on a surface of the conductive layer and having a high dielectric constant. The metal nitride comprises one of niobium, vanadium and compositions thereof. Thus, the EOT and leakage current of the multilayer structure may be sufficiently improved. | 05-05-2011 |
| 20110136317 | Semiconductor device, method of fabricating the same, and semicondutor module, electronic circuit board, and electronic system including the device - Example embodiments relate to a semiconductor device including an oxide dielectric layer and a non-oxide dielectric layer, a method of fabricating the device, and a semiconductor module, an electronic circuit board, and an electronic system including the device. The semiconductor device may include a lower electrode, an oxide dielectric layer disposed on the lower electrode, a non-oxide dielectric layer disposed on the oxide dielectric layer, and an upper electrode disposed on the non-oxide dielectric layer. | 06-09-2011 |
| 20110151639 | SEMICONDUCTOR DEVICE, METHOD OF FABRICATING THE SAME, SEMICONDUCTOR MODULE, ELECTRONIC CIRCUIT BOARD, AND ELECTRONIC SYSTEM INCLUDING THE DEVICE - Provided are a semiconductor device, a method of fabricating the same, and a semiconductor module, an electronic circuit board, and an electronic system including the device. The semiconductor device includes a lower electrode, a rutile state lower vanadium dioxide layer on the lower electrode, a rutile state titanium oxide on the lower vanadium dioxide layer, and an upper electrode on the titanium oxide layer. | 06-23-2011 |
| Patent application number | Description | Published |
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| 20090130457 | DIELECTRIC STRUCTURE - A dielectric structure includes a first dielectric layer, a buffer oxide layer and a second dielectric layer. The lower dielectric layer has a material having a perovskite structure including titanium and is formed on a substrate. The buffer oxide layer is formed on the first dielectric layer. The second dielectric layer has a perovskite structure including titanium and is formed on the buffer oxide layer. | 05-21-2009 |
| 20090258470 | Method of Manufacturing a Semiconductor Device Using an Atomic Layer Deposition Process - Methods of manufacturing a semiconductor device include forming an absorption layer on a surface of a substrate by exposing the surface of the substrate to a first reaction gas at a first temperature. A metal oxide layer is then formed on the surface of the substrate by exposing the absorption layer to a second reaction gas at a second temperature. The first reaction gas may include a precursor containing zirconium (e.g., tetrakis(ethylmethylamino)zirconium) and the second reaction gas may include an oxidizing agent. | 10-15-2009 |
| 20090309187 | Semiconductor Device and Method of Fabricating the Same - Provided is a semiconductor device including a multi-layer dielectric structure and a method of fabricating the semiconductor device. According to one example embodiment, the semiconductor device includes a capacitor comprising: first and second electrodes facing each other; at least one first dielectric layer that is disposed between the first and second electrodes, the at least one first dielectric layer comprising a first high-k dielectric layer doped with silicon; and at least one second dielectric layer that is disposed between the at least one first dielectric layer and any of the first and second electrodes, the at least one second dielectric layer having a higher crystallization temperature than that of the first dielectric layer. | 12-17-2009 |
| 20100047988 | METHODS OF FORMING A LAYER, METHODS OF FORMING A GATE STRUCTURE AND METHODS OF FORMING A CAPACITOR - In a method of forming a layer, a precursor including a metal and a ligand coordinating to the metal is stabilized by contacting the precursor with an electron donating compound to provide a stabilized precursor into a substrate. A reactant is introduced into the substrate to bind to the metal in the stabilized precursor. The precursor stabilized by the electron donating compound has an improved thermal stability and thus the precursor is not dissociated at a high temperature atmosphere, and the layer having a uniform thickness is formed on the substrate. | 02-25-2010 |
| 20100117194 | METAL-INSULATOR-METAL CAPACITORS WITH A CHEMICAL BARRIER LAYER IN A LOWER ELECTRODE - A metal-insulator-metal (MIM) capacitor includes a lower electrode, a dielectric layer, and an upper electrode. The lower electrode includes a first conductive layer, a chemical barrier layer on the first conductive layer, and a second conductive layer on the chemical barrier layer. The chemical barrier layer is between the first and second conductive layers and is a different material than the first and second conductive layers. The dielectric layer is on the lower electrode. The upper electrode is on the dielectric layer opposite to the lower electrode. The first and second conductive layers can have the same thickness. The chemical barrier layer can be thinner than each of the first and second conductive layers. Related methods are discussed. | 05-13-2010 |
| 20100187655 | Integrated Circuit Capacitors Having Composite Dielectric Layers Therein Containing Crystallization Inhibiting Regions and Methods of Forming Same - Integrated circuit capacitors have composite dielectric layers therein. These composite dielectric layers include crystallization inhibiting regions that operate to increase the overall crystallization temperature of the composite dielectric layer. An integrated circuit capacitor includes first and second capacitor electrodes and a capacitor dielectric layer extending between the first and second capacitor electrodes. The capacitor dielectric layer includes a composite of a first dielectric layer extending adjacent the first capacitor electrode, a second dielectric layer extending adjacent the second capacitor electrode and an electrically insulating crystallization inhibiting layer extending between the first and second dielectric layers. The electrically insulating crystallization inhibiting layer is formed of a material having a higher crystallization temperature characteristic relative to the first and second dielectric layers. | 07-29-2010 |
