| Patent application number | Description | Published |
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| 20090101984 | Semiconductor device having gate electrode including metal layer and method of manufacturing the same - A semiconductor device may include a gate dielectric film on a semiconductor substrate and/or a gate electrode. The gate electrode may include a first metal film, a first metal silicide film, and/or a conductive polysilicon film sequentially stacked on the gate dielectric film. | 04-23-2009 |
| 20090189229 | Semiconductor devices and methods of fabricating the same - Provided are semiconductor devices and methods of fabricating the same, and more specifically, semiconductor devices having a W—Ni alloy thin layer that has a low resistance, and methods of fabricating the same. The semiconductor devices include the W—Ni alloy thin layer. The weight of Ni in the W—Ni alloy thin layer may be in a range from approximately 0.01 to approximately 5.0 wt % of the total weight of the W—Ni alloy thin layer. | 07-30-2009 |
| 20100120211 | Methods of manufacturing Semiconductor Devices Including PMOS and NMOS Transistors Having Different Gate Structures - A semiconductor device may include a semiconductor substrate having first and second regions. A first gate structure on the first region of the semiconductor substrate may include a metal oxide dielectric layer on the first region of the semiconductor substrate and a first conductive layer on the metal oxide dielectric layer. First and second source/drain regions of a first conductivity type may be provided in the first region of the semiconductor substrate on opposite sides of the first gate structure. A second gate structure on the second region of the semiconductor substrate may include a silicon oxide based dielectric layer and a second conductive layer on the silicon oxide based dielectric layer. First and second source/drain regions of a second conductivity type may be provided in the second region of the semiconductor substrate on opposite sides of the second gate structure, wherein the first and second conductivity types are different. Related methods are also discussed. | 05-13-2010 |
| 20100210105 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE HAVING BURIED WIRING - A method of fabricating a semiconductor device can include forming a trench in a semiconductor substrate, forming a first conductive layer on a bottom surface and side surfaces of the trench, and selectively forming a second conductive layer on the first conductive layer to be buried in the trench. The second conductive layer may be formed selectively on the first conductive layer by using an electroless plating method or using a metal organic chemical vapor deposition (MOCVD) or an atomic layer deposition (ALD) method. | 08-19-2010 |
| 20110003455 | METHODS FOR FABRICATING IMPROVED GATE DIELECTRICS - Disclosed are a variety of methods for increasing the relative thickness in the peripheral or edge regions of gate dielectric patterns to suppress leakage through these regions. The methods provide alternatives to conventional GPDX processes and provide the improved leakage resistance without incurring the degree of increased gate electrode resistance associated with GPDX processes. Each of the methods includes forming a first opening to expose an active area region, forming an oxidation control region on the exposed portion and then forming a second opening whereby a peripheral region free of the oxidation control region is exposed for formation of a gate dielectric layer. The resulting gate dielectric layers are characterized by a thinner central region surrounded or bounded by a thicker peripheral region. | 01-06-2011 |
| 20110189846 | METHODS OF MANUFACTURING NON-VOLATILE MEMORY DEVICES - A method of manufacturing a non-volatile memory device including a tunnel oxide layer, a preliminary charge storing layer and a dielectric layer on a semiconductor layer is disclosed. A first polysilicon layer is formed on the dielectric layer. A barrier layer and a second polysilicon layer are formed on the first polysilicon layer. The second polysilicon layer, the barrier layer, the first polysilicon layer, the dielectric layer, the preliminary charge storing layer and the tunnel oxide layer are patterned to form a tunnel layer pattern, a charge storing layer pattern, a dielectric layer pattern, a first control gate pattern, a barrier layer pattern and a second polysilicon pattern. A nickel layer is formed on the second polysilicon layer. Heat treatment is performed with respect to the second polysilicon pattern and the nickel layer to form a second control gate pattern including NiSi on the barrier layer pattern. | 08-04-2011 |
| Patent application number | Description | Published |
|---|
| 20090239368 | Methods of Forming an Oxide Layer and Methods of Forming a Gate Using the Same - An oxide layer is selectively formed on a layer including silicon by a plasma process using hydrogen gas and a gas including oxygen. The hydrogen gas is controlled to have a flow rate less than about 50 percent of an overall flow rate by adding helium gas to the plasma process. | 09-24-2009 |
| 20090256177 | Semiconductor device including an ohmic layer - In an ohmic layer and methods of forming the ohmic layer, a gate structure including the ohmic layer and a metal wiring having the ohmic layer, the ohmic layer is formed using tungsten silicide that includes tungsten and silicon with an atomic ratio within a range of about 1:5 to about 1:15. The tungsten silicide may be obtained in a chamber using a reaction gas including a tungsten source gas and a silicon source gas by a partial pressure ratio within a range of about 1.0:25.0 to about 1.0:160.0. The reaction gas may have a partial pressure within a range of about 2.05 percent to about 30.0 percent of a total internal pressure of the chamber. When the ohmic layer is employed for a conductive structure, such as a gate structure or a metal wiring, the conductive structure may have a reduced resistance. | 10-15-2009 |
| 20090315091 | GATE STRUCTURE, AND SEMICONDUCTOR DEVICE HAVING A GATE STRUCTURE - A gate structure can include a polysilicon layer, a metal layer on the polysilicon layer, a metal silicide nitride layer on the metal layer and a silicon nitride mask on the metal silicide nitride layer | 12-24-2009 |
| 20100029073 | Methods of Forming Integrated Circuit Devices Having Anisotropically-Oxidized Nitride Layers - Methods of forming integrated circuit devices include forming a gate electrode on a substrate and forming a nitride layer on a sidewall and upper surface of the gate electrode. The nitride layer is then anisotropically oxidized under conditions that cause a first portion of the nitride layer extending on the upper surface of the gate electrode to be more heavily oxidized relative to a second portion of the nitride layer extending on the sidewall of the gate electrode. A ratio of a thickness of an oxidized first portion of the nitride layer relative to a thickness of an oxidized second portion of the nitride layer may be in a range from about 3:1 to about 7:1. | 02-04-2010 |
