Patent application number | Description | Published |
20090097214 | Electronic chip embedded circuit board and method of manufacturing the same - Provided is a method of manufacturing a device-embedded circuit board. The method includes: preparing a first substrate with a first pattern portion comprising a conductive material; coupling, for example, an electronic chip to the first substrate; preparing a second substrate with a first through hole corresponding to a part of the first pattern portion, a housing portion for housing the electronic chip, and a first connection portion comprising a conductive material formed in the first through hole; preparing a third substrate with a second through hole corresponding to the first through hole and a second connection portion comprising a conductive material formed in the second through hole; aligning and coupling the first, second and third substrates so that the first pattern portion, the first connection portion and the second connection portion are electrically connected. | 04-16-2009 |
20090251962 | Three-Dimensional Memory Device and Driving Method Thereof - A driving method of a three-dimensional memory device having a plurality of layers is provided. One of the layers is selected. A well of the selected layer is biased with a first well voltage. A word line voltage is applied to a selected word line of the selected layer. A well of an unselected layer is biased with a second well voltage higher than the first well voltage. | 10-08-2009 |
20090315187 | Semiconductor device - A semiconductor device includes a lower semiconductor layer with first conductive regions and including at least one dummy first conductive region, an upper semiconductor layer with second conductive regions on the lower semiconductor layer and including at least one dummy second conductive region, a penetration hole in the upper semiconductor layer and penetrating the dummy second conductive region and the upper semiconductor layer under the dummy second conductive region, a lower conductive line on the lower semiconductor layer and electrically connected to the first conductive regions, an upper conductive line on the upper semiconductor layer and electrically connected to the second conductive regions, and a first conductive plug in the penetration hole between the lower conductive line and the upper conductive line, the first conductive plug electrically connecting the lower and upper conductive lines and being spaced apart from sidewalls of the penetration hole. | 12-24-2009 |
20100001337 | Semiconductor memory device - A semiconductor memory device includes: sequentially stacked first and second semiconductor layers; at least one first memory transistor disposed on the first semiconductor layer; and at least one second memory transistor disposed on the second semiconductor layer, wherein a gate electrode of the first memory transistor has a broader width than that of the second memory transistor. | 01-07-2010 |
20100035386 | Method for forming semiconductor device having metallization comprising select lines, bit lines and word lines - A semiconductor device includes a semiconductor substrate including a first region having a cell region and a second region having a peripheral circuit region, first transistors on the semiconductor substrate, a first protective layer covering the first transistors, a first insulation layer on the first protective layer, a semiconductor pattern on the first insulation layer in the first region, second transistors on the semiconductor pattern, a second protective layer covering the second transistors, the second protective layer having a thickness greater than that of the first protective layer, and a second insulation layer on the second protective layer and the first insulation layer of the second region. | 02-11-2010 |
20100046294 | NON-VOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A non-volatile memory device includes first and second strings memory cell transistors, related first and second word lines respectively connected to gates of the first string memory cell transistors, wherein respective first and second word lines are connected to commonly receive a bias voltage. The non-volatile memory device also includes dummy cell transistors connected to the first and second strings, and first and second dummy word lines configured to receive different bias voltages. | 02-25-2010 |
20100046304 | NON-VOLATILE MEMORY DEVICE AND ERASE METHOD - Provided is a non-volatile memory device including first and second, vertically stacked semiconductor substrates, a plurality of non-volatile memory cell transistors formed in a row on the first and second semiconductor substrates, and a plurality of word lines connected to gates of the plurality of non-volatile memory cell transistors. The plurality of non-volatile memory cell transistors are grouped into two or more memory cell blocks, such that a first voltage is applied to the first semiconductor substrate including a first memory cell block to be erased, and either (1) a second voltage less than the first voltage and greater than 0V is applied to the second semiconductor substrate not including the first memory cell block, or (2) the second semiconductor substrate not including the first memory cell block is allowed to electrically float. | 02-25-2010 |
20100195395 | Non-volatile memory device having vertical structure and method of operating the same - A non-volatile memory device having a vertical structure includes a NAND string having a vertical structure. The NAND string includes a plurality of memory cells, and at least one pair of first selection transistors arranged to be adjacent to a first end of the plurality of memory cells. A plurality of word lines are coupled to the plurality of memory cells of the NAND string. A first selection line is commonly connected to the at least one pair of first selection transistors of the NAND string. | 08-05-2010 |
20110002178 | VERTICAL NON-VOLATILE MEMORY DEVICE, METHOD OF FABRICATING THE SAME DEVICE, AND ELECTRIC-ELECTRONIC SYSTEM HAVING THE SAME DEVICE - Provided is a vertical non-volatile memory device having a metal source line. The vertical non-volatile memory device includes cell string units that are formed on first portions of a semiconductor substrate and are vertically arranged with respect to a surface of the semiconductor substrate, impurity regions formed on second portions of the semiconductor substrate between the cell string units, conductive lines formed on the impurity regions, and spacers that are formed on the sidewalls of the cell string units and insulate the conductive lines from the cells string units. | 01-06-2011 |
20110018036 | VERTICAL NON-VOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A vertical non-volatile memory device is structured/fabricated to include a substrate, groups of memory cell strings each having a plurality of memory transistors distributed vertically so that the memory throughout multiple layers on the substrate, integrated word lines coupled to sets of the memory transistors, respectively, and stacks of word select lines. The memory transistors of each set are those transistors, of one group of the memory cell strings, which are disposed in the same layer above the substrate. The word select lines are respectively connected to the integrated word lines. | 01-27-2011 |
20110019486 | SEMICONDUCTOR MEMORY DEVICE AND PROGRAMMING METHOD THEREOF - A programming method of a semiconductor memory device includes charging a channel of an inhibit string to a precharge voltage provided to the common source line and boosting the charged channel by providing a wordline voltage to the cell strings. The inhibit string is connected to a program bitline among the bitlines. | 01-27-2011 |
20110024816 | FLASH MEMORY DEVICE HAVING VERTICLE CHANNEL STRUCTURE - A flash memory device having a vertical channel structure. The flash memory device includes a substrate having a surface that extends in a first direction, a channel region having a pillar shape and extending from the substrate in a second direction that is perpendicular to the first direction, a gate dielectric layer formed around the channel region, a memory cell string comprising a plurality of transistors sequentially formed around the channel region in the second direction, wherein the gate dielectric layer is disposed between the plurality of transistors and the channel region, and a bit line connected to one of the plurality of transistors, and surrounding a side wall and an upper surface of one end of the channel region so as to directly contact the channel region. | 02-03-2011 |
20110227141 | NON-VOLATILE MEMORY DEVICES HAVING VERTICAL CHANNEL STRUCTURES AND RELATED FABRICATION METHODS - A memory device having a vertical channel structure is disclosed. The memory device includes a plurality of gate lines extending substantially parallel to one another along a surface of a substrate, and a connection unit electrically connecting the plurality of gate lines. The connection unit includes a first portion laterally extending along the surface of the substrate, a second portion extending substantially perpendicular to the surface of the substrate, and a supporting insulating layer extending in a cavity defined by the first and second portions of the connection unit. Related fabrication methods are also discussed. | 09-22-2011 |
20120009767 | METHOD FOR FORMING SEMICONDUCTOR DEVICE HAVING METALLIZATION COMPRISING SELECT LINES, BIT LINES AND WORD LINES - A semiconductor device includes a semiconductor substrate including a first region having a cell region and a second region having a peripheral circuit region, first transistors on the semiconductor substrate, a first protective layer covering the first transistors, a first insulation layer on the first protective layer, a semiconductor pattern on the first insulation layer in the first region, second transistors on the semiconductor pattern, a second protective layer covering the second transistors, the second protective layer having a thickness greater than that of the first protective layer, and a second insulation layer on the second protective layer and the first insulation layer of the second region. | 01-12-2012 |
20120077320 | MANUFACTURING SEMICONDUCTOR DEVICES - A semiconductor device includes a semiconductor pattern on a substrate, gate structures on sidewalls of the semiconductor pattern, the gate structures being spaced apart from one another, insulating interlayers among the gate structures, wherein an uppermost insulating interlayer is lower than an upper face of the semiconductor pattern, a common source line contacting the substrate and protruding above the uppermost insulating interlayer, an etch stop layer pattern on the semiconductor pattern and on the common source line wherein the common source line protrudes above the uppermost insulating interlayer, an additional insulating interlayer on the uppermost insulating interlayer, and contact plugs extending through the additional insulating interlayer so as to make contact with the semiconductor pattern and the common source line, respectively. | 03-29-2012 |
20120098048 | VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A vertical memory device includes a channel, a ground selection line (GSL), word lines and a string selection line (SSL). The channel extends in a first direction substantially perpendicular to a top surface of a substrate, and a thickness of the channel is different according to height. The GSL, the word lines and the SSL are sequentially formed on a sidewall of the channel in the first direction and spaced apart from each other. | 04-26-2012 |
20130044545 | NON-VOLATILE MEMORY DEVICE HAVING VERTICAL STRUCTURE AND METHOD OF OPERATING THE SAME - A non-volatile memory device having a vertical structure includes a NAND string having a vertical structure. The NAND string includes a plurality of memory cells, and at least one pair of first selection transistors arranged to be adjacent to a first end of the plurality of memory cells. A plurality of word lines are coupled to the plurality of memory cells of the NAND string. A first selection line is commonly connected to the at least one pair of first selection transistors of the NAND string. | 02-21-2013 |
20130242667 | NON-VOLATILE MEMORY DEVICES, OPERATING METHODS THEREOF AND MEMORY SYSTEMS INCLUDING THE SAME - Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines. | 09-19-2013 |
20130279233 | VERTICAL NON-VOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A vertical non-volatile memory device is structured/fabricated to include a substrate, groups of memory cell strings each having a plurality of memory transistors distributed vertically so that the memory throughout multiple layers on the substrate, integrated word lines coupled to sets of the memory transistors, respectively, and stacks of word select lines. The memory transistors of each set are those transistors, of one group of the memory cell strings, which are disposed in the same layer above the substrate. The word select lines are respectively connected to the integrated word lines. | 10-24-2013 |
20140016413 | NONVOLATILE MEMORY DEVICE, OPERATING METHOD THEREOF, AND MEMORY SYSTEM INCLUDING THE SAME - Provided is a method of operating a nonvolatile memory device that includes a substrate and memory blocks having a plurality of memory cells stacked along a direction perpendicular to the substrate. The method includes: reading data from a selected sub block among sub blocks of a selected memory block and selectively refreshing each sub block of the selected memory block in response to the reading of the selected sub block, wherein each sub block of the selected memory block is separately erased. | 01-16-2014 |
20140048873 | SEMICONDUCTOR DEVICES - A semiconductor device includes a semiconductor pattern on a substrate, gate structures on sidewalls of the semiconductor pattern, the gate structures being spaced apart from one another, insulating interlayers among the gate structures, wherein an uppermost insulating interlayer is lower than an upper face of the semiconductor pattern, a common source line contacting the substrate and protruding above the uppermost insulating interlayer, an etch stop layer pattern on the semiconductor pattern and on the common source line wherein the common source line protrudes above the uppermost insulating interlayer, an additional insulating interlayer on the uppermost insulating interlayer, and contact plugs extending through the additional insulating interlayer so as to make contact with the semiconductor pattern and the common source line, respectively. | 02-20-2014 |
20140293703 | NON-VOLATILE MEMORY DEVICE HAVING VERTICAL STRUCTURE AND METHOD OF OPERATING THE SAME - A non-volatile memory device having a vertical structure includes a NAND string having a vertical structure. The NAND string includes a plurality of memory cells, and at least one pair of first selection transistors arranged to be adjacent to a first end of the plurality of memory cells. A plurality of word lines are coupled to the plurality of memory cells of the NAND string. A first selection line is commonly connected to the at least one pair of first selection transistors of the NAND string. | 10-02-2014 |