| Patent application number | Description | Published |
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| 20080307980 | SHAPING APPARATUS FOR FRUITS AND ROOT AND TUBEROUS VEGETABLES - An apparatus is disclosed which can shape fruits and root and tuberous vegetables. The shaping apparatus is operated in such a manner that: when root and tuberous vegetable or fruit is placed in a cutting blade case and rotated, the object is spirally tracked and the spirally tracked object is removed from the lower side of the cutting blade case, so that the spirally tracked object is picked up by an additional stick and then ornamented into various forms. The shaping apparatus allows fruits and root and tuberous vegetables to be easily treated in a variety of ways, as per the second process, thereby enhancing the product value of processed foodstuffs produced from the first process. | 12-18-2008 |
| 20090089321 | Method and system for managing social brokering services in an online social network - A method and system for managing social brokering services in an online social network has developed that is comprising: social network database storing member information, human network information by member information on basis of a social network, and Needs information; an application server converting written Needs request into Needs information and storing it as said social network database after making payment of charges for use when the written Needs request for solving problems is inputted from Social Brokering Users, acting as members, providing Needs proposal with Social Brokering Users when the written Needs proposal is conveyed from Social Brokers, members, making payment of the amount according to types of dealing, like purchase, sales, exchange, etc., and contracts upon establishing contracts between Social Brokering Users and Social Brokers, and transferring the payment amount upon completing the contract; a Needs server delivering undelivered Needs information to the first human connection according to human network information of Social Brokering Users or Social Forwarders by searching Needs information stored in said social network database; and a payment server processing charges for use and payment when payment is executed in said application server. According to the present invention, it is possible to describe the problem and set up the amount of compensation in case that it is required to resolve various visible and invisible problems each member obtains; to overcome problems of trust and reliance by utilizing connection among people as brokers for assisting settlement of problems in the process of being delivered in accordance with a human network in the online social network if the step of delivering human connection among people is set up, and the amount of compensation(costs for dealing, and brokerage) and charges for use are paid; to support prompt settlement of problems for active anticipation of people, who have an ability to solve problems, from others; to provide costs for solving problems and brokerage in accordance with market forces for people who solve problems and to make the economical compensation granted by distributing brokerage with Needs forwarders in the middle step of human connection; and to form mutual relation during resolving problems. | 04-02-2009 |
| 20090119569 | Encoding system and method for encoding error control codes within bit streams - An encoding system for encoding error control codes may include a first encoder configured to encode an input bit stream to generate first bit streams of C-bits, where c is an integer greater than zero, and a second encoder may be configured to receive the first bit streams and shuffle data of the received first bit streams to generate second bit streams. The data shuffling of the first bit streams may adjust an error distribution of the second bit streams. An encoding method may include encoding an input bit stream to generate first bit streams of C-bits, and receiving the first bit streams and shuffling data of the received first bit streams to generate second bit streams. An error distribution of the second bit streams may be adjusted based on the data shuffling. | 05-07-2009 |
| 20090153271 | VARIABLE RADIO FREQUENCY BAND FILTER - A variable radio frequency band filter capable of varying the resonance frequency band comprises a housing having a support; a number of resonator rods arranged along the longitudinal direction of the housing; at least one tuning rod positioned on top of the resonator rods; a tuning support extending through the respective tuning rods along the longitudinal direction of the housing and adapted to slide on top of the respective resonator rods to vary the position of the tuning rods; and a frequency variation unit positioned on a lateral surface of the housing. The frequency variation unit being coupled to an end of the tuning support and adapted to vary the position of the tuning rods, as the tuning support is slid, according to the frequency band. | 06-18-2009 |
| 20090175076 | Memory device and method for estimating characteristics of multi-bit cell - Memory devices and/or methods that may estimate characteristics of multi-bit cell are provided. A memory device may include: a multi-bit cell array; a monitoring unit to extract a threshold voltage change over time value for reference threshold voltage states selected from a plurality of threshold voltage states corresponding to data stored in the multi-bit cell array; and an estimation unit to estimate a threshold voltage change over time values for the plurality of threshold voltage states based on the extracted threshold voltage change. Through this, it is possible to monitor a change over time of threshold voltages of a memory cell. | 07-09-2009 |
| 20090177931 | Memory device and error control codes decoding method - Memory devices and/or error control codes (ECC) decoding methods may be provided. A memory device may include a memory cell array, and a decoder to perform hard decision decoding of first data read from the memory cell array by a first read scheme, and to generate output data and error information of the output data. The memory device may also include and a control unit to determine an error rate of the output data based on the error information, and to determine whether to transmit an additional read command for soft decision decoding to the memory cell array based on the error rate. An ECC decoding time may be reduced through such a memory device. | 07-09-2009 |
| 20090185417 | Apparatus and method of memory programming - A memory programming apparatuses and/or methods are provided. The memory programming apparatus may include a data storage unit, a first counting unit, an index storage unit and/or a programming unit. The data storage unit may be configured to store a data page. The first counting unit may be configured to generate index information by counting a number of cells included in at least one reference threshold voltage state based on the data page. The index storage unit may be configured to store the generated index information. The programming unit may be configured to store the data page in the data storage unit and store the generated index information in the index storage unit. The first counting unit may send the generated index information to the programming unit. The memory programming apparatus can monitor distribution states of threshold voltages in memory cells. | 07-23-2009 |
| 20090190397 | Memory device and data reading method - A memory device and a memory data reading method are provided. The memory device may include: a multi-bit cell array; a programming unit that stores N data pages in a memory page in the multi-bit cell array; and a control unit that divides the N data pages into a first group and second group, reads data of the first group from the memory page, and determines a scheme of reading data of the second group from the memory page based on the read data of the first group. | 07-30-2009 |
| 20090193313 | Method and apparatus for decoding concatenated code - Provided are apparatuses for decoding a concatenated code and methods for the same that may improve the decoding speed of a concatenated code based on a likelihood value with respect to output from a plurality of decoders. | 07-30-2009 |
| 20090201729 | Memory device and memory device heat treatment method - A memory device and a memory device heat treatment method are provided. The memory device may include: a non-volatile memory device; one or more heating devices configured to contact with the non-volatile memory device and heat the non-volatile memory device; and a controller configured to control an operation of the one or more heating devices based on operational information of the non-volatile memory device. Through this, it may be possible to improve an available period of the non-volatile memory device. | 08-13-2009 |
| 20090207671 | Memory data detecting apparatus and method for controlling reference voltage based on error in stored data - Example embodiments may relate to a method and an apparatus for reading data stored in a memory, for example, providing a method and an apparatus for controlling a reference voltage based on an error of the stored data. Example embodiments may provide a memory data detecting apparatus including a first voltage comparator to compare a threshold voltage of a memory cell with a first reference voltage, a first data determiner to determine a value of at least one data bit stored in the memory cell according to a result of the comparison, an error verifier to verify whether an error occurs in the determined value, a reference voltage determiner to determine a second reference voltage that is lower than the first reference voltage based on a result of the verification, and a second data determiner to re-determine the value of the data based on the determined second reference voltage. | 08-20-2009 |
| 20090210776 | Memory device and memory data reading method - Example embodiments may provide a memory device and memory data reading method. The memory device according to example embodiments may include a multi-bit cell array, an error detector which may read a first data page from a memory page in the multi-bit cell array and may detect an error-bit of the first data page, and an estimator which may identify a multi-bit cell where the error-bit is stored and may estimate data stored in the identified multi-bit cell among data of a second data page. Therefore, the memory device and memory data reading method may have an effect of reducing an error when reading data stored in the multi-bit cell and monitoring a state of the multi-bit cell without additional overhead. | 08-20-2009 |
| 20090222701 | Apparatus for determining number of bits to be stored in memory cell - Example embodiments relate to an apparatus which may determine a length of data to be stored in a memory cell, and may store the data in a memory based on the determined length. A memory data storage apparatus according to example embodiments may, include: a determination unit that may determine a number of bits of data and a number of bits of data detection information to be stored in a memory cell; a data receiving unit that may receive data corresponding to the determined number of bits; an error correction coding unit that may perform an error correction coding with respect to the received data and generate data detection information corresponding to the number of bits of the data detection information; and a data storage unit that may store the received data and generated data detection information in the memory cell. | 09-03-2009 |
| 20090235128 | Data detecting apparatus based on channel information and method thereof - An apparatus and a method for detecting data stored in a memory cell based on channel information of the memory cell are provided. The data detecting apparatus may include a voltage comparison unit that compares a plurality of soft decision reference voltages between neighboring hard decision reference voltages with a threshold voltage of a memory cell to determine a region including the threshold voltage, and a data detection unit that detects data stored in the memory cell based on channel information of the memory cell according to the region. The data detecting apparatus may further include a reference voltage determination unit that determines the plurality of soft decision reference voltages based on the channel information of the memory cell. | 09-17-2009 |
| 20090235129 | Apparatus and method for hybrid detection of memory data - The data detecting apparatus may provide a voltage comparison unit that compares a reference voltage, associated with a specific data bit from among a plurality of data bits stored in a memory cell, with a threshold voltage in the memory cell, a detection unit that detects a value of the specific data bit based on a result of the voltage comparison unit, and a decision unit that decides whether the specific data bit is successfully detected based on whether an error occurs in the detected data. The detection unit may re-detect a value of the specific data bit based on detection information with respect to at least one of an upper data bit and a lower data bit in relation to the specific data bit, in response to a result of the decision unit. | 09-17-2009 |
| 20090241008 | Memory devices and encoding and/or decoding methods - Memory devices and/or encoding/decoding methods are provided. A memory device may include: a memory cell array; an internal decoder configured to apply, to a first codeword read from the memory cell array, a first decoding scheme selected based on a characteristic of a first channel in which the first codeword is read to perform error control codes (ECC) decoding of the first codeword, and apply, to a second codeword read from the memory cell array, a second decoding scheme selected based on a characteristic of a second channel in which the second codeword is read to perform the ECC decoding of the second codeword; and an external decoder configured to apply an external decoding scheme to the ECC-decoded first codeword and the ECC-decoded second codeword to perform the ECC decoding of the first codeword and the second codeword. | 09-24-2009 |
| 20090241009 | Encoding and/or decoding memory devices and methods thereof - Encoding/decoding memory devices and methods thereof may be provided. A memory device according to example embodiments may include a memory cell array and a processor including at least one of a decoder and an encoder. The processor may be configured to adjust a redundant information rate of each channel, where each of the channels is a path of the memory cell array from which data is at least one of stored and read. The redundant information rate may be adjusted by generating at least one codeword based on information from a previous codeword. Therefore, example embodiments may reduce an error rate when data is read from and written to the memory device. | 09-24-2009 |
| 20090276687 | METHOD OF ENCODING AND DECODING MULTI-BIT LEVEL DATA - A method of encoding multi-bit level data includes: determining a range of an error pattern generated according to a transmission symbol, encoding an M-bit level of a P-bit level corresponding to the transmission symbol based on the range of the error pattern, and excluding encoding of a P-M bit level of the P-bit level. The variable P is a natural number of a value at least two, and the variable M is a natural number less than P. | 11-05-2009 |
| 20090282319 | HIERARCHICAL DECODING APPARATUS - A decoder includes multiple decoder stages and a controller. The decoder stages perform decoding operations with respect to a received signal using corresponding different decoding algorithms. The controller determines whether the decoding operation performed by one of the decoder stages with respect to the received signal is successful, and controls the decoding operation of each of the other decoder stages in response to a result of the determination. | 11-12-2009 |
| 20090287975 | Memory device and method of managing memory data error - Memory devices and/or methods of managing memory data errors are provided. A memory device detects and corrects an error bit of data read from a plurality of memory cells, and identifies a memory cell storing the detected error bit. The memory device assigns a verification voltage to each of the plurality of first memory cells, the assigned verification voltage corresponding to the corrected bit for the identified memory cell, the assigned verification voltage corresponding to the read data for the remaining memory cells. The memory device readjusts the data stored in the plurality of memory cells using the assigned verification voltage. Through this, it is possible to increase a retention period of the data of the memory device. | 11-19-2009 |
| 20090289172 | DETECTION OF SEED LAYERS ON A SEMICONDUCTOR DEVICE - A device and/or method which detects a seed layer and a device and/or method of forming layers on a semiconductor device. The device which forms layers on the semiconductor device may include a metal layer forming unit (which forms a metal layer on a wafer), a copper seed layer forming unit (which forms a copper seed layer on the metal layer), a wafer alignment device (which includes a wafer alignment unit which aligns the wafer to a predetermined position), a copper seed layer detecting unit (which is positioned above the wafer alignment unit to detect the copper seed layer formed on the wafer), and a plating unit (which forms a copper interconnection layer on the copper seed layer). | 11-26-2009 |
| 20090296466 | Memory device and memory programming method - Provided are memory devices and memory programming methods. A memory device may include: a multi-bit cell array that includes a plurality of memory cells; a controller that extracts state information of each of the memory cells, divides the plurality of memory cells into a first group and a second group, assigns a first verify voltage to memory cells of the first group and assigns a second verify voltage to memory cells of the second group; and a programming unit that changes a threshold voltage of each memory cell of the first group until the threshold voltage of each memory cell of the first group is greater than or equal to the first verify voltage, and changes a threshold voltage of each memory cell of the second group until the threshold voltage of each memory cell of the second group is greater than or equal to the second verify voltage. | 12-03-2009 |
| 20090296486 | Memory device and memory programming method - Memory devices and/or memory programming methods are provided. A memory device may include: a memory cell array including a plurality of memory cells; a programming unit configured to apply a plurality of pulses corresponding to a program voltage to a gate terminal of each of the plurality of memory cells, and to apply a program condition voltage to a bit line connected with a memory cell having a threshold voltage lower than a verification voltage from among the plurality of memory cells; and a control unit configured to increase the program voltage during a first time interval by a first increment for each pulse, and to increase the program voltage during a second time interval by a second increment for each pulse. Through this, it may be possible to reduce a width of a distribution of threshold voltages of a memory cell. | 12-03-2009 |
| 20090307566 | ITERATIVE DECODING METHOD AND APPARATUS - An iterative decoding method is disclosed and includes sequentially executing a number of iterative decoding cycles in relation to a parity check equation until the parity check equation is resolved, or a maximum number N of iterative decoding cycles is reached, during execution of the number of iterative decoding cycles, storing in a data buffer minimum estimated values for a set of variable nodes corresponding to a minimum number of bit errors, and outputting the minimum estimated values stored in the data buffer as a final decoding result when the number of iterative decoding cycles reaches N. | 12-10-2009 |
| 20090323156 | Method of forming electrochromic layer pattern, method of manufacturing electrochromic device using the same, and electrochromic device including electrochromic layer pattern - A method for forming an electrochromic layer pattern includes forming a transparent electrode layer and a photoresist layer on a transparent substrate, forming a photoresist pattern by laser interference lithography, and depositing an electrochromic layer pattern on the transparent electrode through openings defined by the photoresist pattern by depositing an electrochromic layer on a front surface of the substrate and then lifting up the photoresist pattern. An insulation layer may be further formed between the transparent layer and the photoresist layer. Here, the electrochromic layer may be formed after an insulation layer pattern is formed using the photoresist pattern as an etching mask. In this case, the electrochromic layer pattern is formed in openings defined by the insulation layer pattern. As a result, a contact surface area between the electrochromic layer pattern and the ion conductive layer is increased to ensure a rapid response speed. | 12-31-2009 |
| 20100008146 | Memory device and method of programming thereof - The method of programming data in a memory device includes applying a plurality of pulses to a plurality of memory cells, at least one of the plurality of pulses being a positive pulse having a positive voltage and at least one of the plurality of pulses being a negative pulse having a negative voltage, and a temporal interval existing between subsequent pulses of the plurality of pulses, and controlling at least one of a width of at least one of the temporal intervals and a magnitude of at least one of the plurality of pulses. | 01-14-2010 |
| 20100014145 | ELECTRODE COMPRISING LITHIUM NICKEL OXIDE LAYER, METHOD FOR PREPARING THE SAME, AND ELECTROCHROMIC DEVICE COMPRISING THE SAME - Disclosed is a method of preparing an electrode, which can lead to uniform electrochromism of a lithium nickel oxide layer by applying a voltage in all directions of the electrode during a formatting process, an electrode prepared by the same, and an electrochromic device including the electrode. | 01-21-2010 |
| 20100020620 | Memory device and method of programming thereof - Example embodiments may provide a memory device and memory data programming method. The memory device according to example embodiments may encode a first data page to generate at least one first codeword and encode a second data page to generate a second codeword. The memory device may generate the first codeword with at least one of a maximum value of a number of successive ones and a second maximum value of a number of successive zeros. The memory device may program the at least one first codeword and the at least one second codeword to a plurality of multi-bit cells. | 01-28-2010 |
| 20100027335 | Memory device and wear leveling method - The memory device selects any one of a first memory cell and a second memory cell based on a number of times that the first memory cell is erased, an elapsed time after the first memory cell is erased, a number of times that the second memory cell is erased, and an elapsed time after the second memory cell is erased, and program data in the selected memory cell. The memory device may improve distribution of threshold voltage of memory cells and endurance of the memory cells. | 02-04-2010 |
| 20100027342 | Memory device and memory data determination method - A memory device and a memory data determination method are provided. The memory device may estimate a threshold voltage shift of a first memory cell based on data before the first memory cell is programmed and a target program threshold voltage of the first memory cell. The memory device may generate a metric of a threshold voltage shift of a second memory cell based on the estimated threshold voltage shift of the first memory cell. Also, the memory device may determine data stored in the second memory cell based on the metric. | 02-04-2010 |
| 20100088574 | DATA STORAGE SYSTEM AND DEVICE WITH RANDOMIZER/DE-RANDOMIZER - A data storage device receives write data and includes a controller configured to determine a characteristic of the write data and provide a first control signal in response to the determined characteristic, a randomizer configured to selectively randomize or not randomize the write data in response to the first control signal to thereby generate randomized write data, and a data storage unit configured to store the randomized write data. | 04-08-2010 |
| 20100091578 | Nonvolatile Memory Devices Having Built-in Memory Cell Recovery During Block Erase and Methods of Operating Same - Nonvolatile memory devices include support memory cell recovery during operations to erase blocks of nonvolatile (e.g., flash) memory cells. A nonvolatile memory system includes a flash memory device and a memory controller electrically coupled to the flash memory device. The memory controller is configured to control memory cell recovery operations within the flash memory device by issuing a first instruction(s) to the flash memory device that causes erased memory cells in the block of memory to become at least partially programmed memory cells and then issuing a second instruction(s) to the flash memory device that causes the at least partially programmed memory cells become fully erased. | 04-15-2010 |
| 20100174959 | DECODING METHOD AND MEMORY SYSTEM DEVICE USING THE SAME - A decoding method includes performing a first decoding method and performing a second decoding method when decoding of the first decoding method fails. The first decoding method includes updating multiple variable nodes and multiple check nodes using probability values of received data. The second decoding method includes selecting at least one variable node from among the multiple variable nodes; correcting probability values of data received in the selected at least one variable node; updating the variable nodes and the check nodes using the corrected probability values; and determining whether decoding of the second decoding method is successful. | 07-08-2010 |
| 20100174966 | DEVICE AND METHOD PROVIDING 1-BIT ERROR CORRECTION - A 1-bit error correction method is provided. In the method, a variable node at which an error has occurred is detected based on a number of unsatisfied check nodes that do not satisfy a parity condition among check nodes connected to each of variable nodes and an error in a bit corresponding to the detected variable node is corrected. | 07-08-2010 |
| 20100212109 | HINGE DAMPER - The present invention relates to a hinge damper and, more particularly, to a hinge damper that is configured to be adhered to a door hinge of the furniture having a door to attenuate impact and is designed in a small size but to attenuate a large amount of impact. In a hinge damper of the present invention, first and second seals are formed in an oil seal to prevent air from being introduced. A cross rib is formed on a piston to absorb a larger amount of impact with a small size. According to the present invention, the hinge damper can be small-sized while attenuating impact the present invention has been made. In addition, the hinge damper does not affect on the size of the hinge. Further, since the hinge damper can be identically sized to a screw used for fixing the hinge, it is not exposed to an external side. | 08-26-2010 |
| 20100230679 | CONTACT PORTION OF WIRE AND MANUFACTURING METHOD THEREOF - A contact portion of wiring and a method of manufacturing the same are disclosed. A contact portion of wiring according to an embodiment includes: a substrate; a conductive layer disposed on the substrate; an interlayer insulating layer disposed on the conductive layer and having a contact hole; a metal layer disposed on the conductive layer and filling the contact hole; and a transparent electrode disposed on the interlayer insulating layer and connected to the metal layer, wherein the interlayer insulating layer includes a lower insulating layer and an upper insulating layer disposed on the lower insulating layer, the lower insulating layer is undercut at the contact hole, and the metal layer fills in the portion where the lower insulating layer is undercut. | 09-16-2010 |
| 20100251077 | STORAGE DEVICE AND DATA STORAGE SYSTEM INCLUDING OF THE SAME - A storage device includes a controller unit and a memory cell array. The controller unit is for outputting data through a first data path or a second data path according to a property of externally supplied input data. The memory cell array includes a first memory and a second memory, and receives and stores the data from the controller unit output through the first and second data paths. The first memory has a different memory cell structure than the second memory. | 09-30-2010 |
| 20100254189 | Apparatus and method of memory programming - A memory programming apparatuses and/or methods are provided. The memory programming apparatus may include a data storage unit, a first counting unit, an index storage unit and/or a programming unit. The data storage unit may be configured to store a data page. The first counting unit may be configured to generate index information by counting a number of cells included in at least one reference threshold voltage state based on the data page. The index storage unit may be configured to store, the generated index information. The programming unit may be configured to store the data page in the data storage unit and store the generated index information in the index storage unit. The first counting unit may send the generated index information to the programming unit. The memory programming apparatus can monitor distribution states of threshold voltages in memory cells. | 10-07-2010 |
| 20100254195 | Memory device and method for estimating characteristics of multi-bit programming - Memory devices and/or methods that may estimate characteristics of multi-bit cell are provided. A memory device may include: a multi-bit cell array; a monitoring unit to extract a threshold voltage change over time value for reference threshold voltage states selected from a plurality of threshold voltage states corresponding to data stored in the multi-bit cell array; and an estimation unit to estimate a threshold voltage change over time values for the plurality of threshold voltage states based on the extracted threshold voltage change. Through this, it is possible to monitor a change over time of threshold voltages of a memory cell. | 10-07-2010 |
| 20100270552 | THIN FILM TRANSISTOR SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A protrusion of dry-etched pattern of a thin film transistor substrate generated due to a difference between isotropy of wet etching and anisotropy of dry etching is removed by forming a plating part on a surface of the wet etched pattern through an electroless plating method. If the plating part is formed on a data pattern layer of the substrate, the width or the thickness of the data pattern layer may be increased without loss of aperture ratio, the channel length of the semiconductor layer may be reduced under the limit according to the stepper resolution and the protrusion part of the semiconductor layer may be removed. As a result, the aperture ratio may be increased, the resistance may be reduced, and the driving margin may be increased due to rising of the ion current. Furthermore, the so-called water-fall noise phenomenon may be eliminated. | 10-28-2010 |
| 20100287447 | MEMORY SYSTEM IDENTIFYING AND CORRECTING ERASURE USING REPEATED APPLICATION OF READ OPERATION - Provided is a read method for a memory system. The read method determines whether a read data error is correctable. The read method applies a plurality of read operations at a set read voltage level to identify erasure candidates, when the error is uncorrectable. The read method performs erasure decoding using an error correction code or an error detection code for the erasure candidates. | 11-11-2010 |
| 20100296350 | METHOD OF SETTING READ VOLTAGE MINIMIZING READ DATA ERRORS - A method setting a read voltage to minimize data read errors in a semiconductor memory device including multi-bit memory cells. In the method, a read voltage associated with a minimal number of read data error is set based on a statistic value of a voltage distribution corresponding to each one of a plurality of voltage states. | 11-25-2010 |
| 20100321999 | NONVOLATILE MEMORY DEVICE AND RELATED PROGRAMMING METHOD - A method of programming a nonvolatile memory device comprises programming memory cells connected to a first wordline, programming memory cells connected to a second wordline, programming memory cells connected to a third line between the first wordline and the second wordline, and adjusting a threshold voltage of the memory cells connected to the first wordline to compensate for interference generated by the programming of the memory cells connected to the third wordline. | 12-23-2010 |
| 20110032759 | MEMORY SYSTEM AND RELATED METHOD OF PROGRAMMING - A method of programming a nonvolatile memory device comprises counting a number of state pairs in a unit of input data, modulating the unit of input data to reduce the number of state pairs contained therein, and programming the modulated unit of input data in the nonvolatile memory device. Each state pair comprises data with a first state and designated for programming in a memory cell connected to a first word line, and data with a second state and designated for programming in a memory cell connected to a second word line adjacent to the first word line. The memory cell connected to the first word line is adjacent to the memory cell connected to the second word line. | 02-10-2011 |
| 20110038207 | FLASH MEMORY DEVICE, PROGRAMMING AND READING METHODS PERFORMED IN THE SAME - The flash memory device includes a control logic circuit and a bit level conversion logic circuit. The control logic circuit programs first through N | 02-17-2011 |
| 20110040929 | METHOD AND APPARATUS FOR MODIFYING DATA SEQUENCES STORED IN MEMORY DEVICE - A method of modifying data sequences in a memory system comprises receiving program data having a first data sequence, and determining whether the received first data sequence matches one of “m” predefined sequences stored in the memory system. The method further comprises replacing the received first data sequence with a replacement sequence upon determining that the received first data sequence matches one of the “m” predefined sequences, and outputting the replacement sequence from the memory system. The replacement sequence typically comprises pattern bits indicating a pattern of the first data sequence and location bits indicating a start location of the first data sequence. | 02-17-2011 |
| 20110047432 | APPARATUS AND METHOD FOR CODING IN COMMUNICATION SYSTEM - Disclosed is a method and apparatus for coding in a communication system. The coding method includes generating an information codeword vector from an information vector, generating a first vector in the information vector from an information part of a parity check matrix, generating a first parity codeword vector by performing an exclusive OR operation of the first vector and a second vector corresponding to a cyclically shifted version of the first vector, and generating a second parity codeword vector by performing an exclusive OR operation of the first vector, the first parity codeword vector, and a third vector. The third vector is a cyclically shifted version of a vector resulting from the exclusive OR operation of the first vector, the first parity codeword vector, and a fed-back third vector. | 02-24-2011 |
| 20110051057 | LIQUID CRYSTAL DISPLAY AND MANUFACTURING METHOD THEREOF - The present invention relates to a liquid crystal display, wherein arrangement of liquid crystal molecules thereof is controlled by using a monomer that is polymerized by ultraviolet rays to provide a pre-tilt. To prevent damage to organic material layers when irradiating ultraviolet rays to the monomer, a blocking film made of an ultraviolet absorbing agent is formed on or over at least one such layer. | 03-03-2011 |
