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| 20090171575 | NAVIGATION APPARATUS AND METHOD FOR PROVIDING TURN-BY-TURN POSITION LIST - The present invention relates to a navigation apparatus and a method for providing a user with a list of turn-by-turn positions (TBTs) located ahead on a route. The navigation apparatus of the present invention according to an embodiment comprises a GPS receiving module for receiving navigation satellite signals and calculating a position; a controller for receiving position information from the GPS receiving module, outputting the position information together with map information, and controlling operation of the GPS receiving module; and a storage unit for storing the map information, wherein the controller displays information on two or more TBTs on a proceeding route in the form of a list, the list having a size determined depending on distances to the TBTs included in the TBT information. According to the present invention, there are advantages in that a user can easily recognize information on TBTs ahead and drive a vehicle along a set route only with a TBT list. | 07-02-2009 |
| 20090171576 | NAVIGATION APPARATUS AND METHOD OF PROVIDING INFORMATION ON POINTS OF INTEREST - An apparatus of providing map information, which includes a Global Positioning System (GPS) receiving module configured to calculate positional information with respect to the apparatus, a display configured to display map information and the calculated positional information, and a controller configured to search for Points of Interests (POIs) from a selected POI category, and to control the display to display image icons representing POIs that were found during the search on corresponding positions within the displayed map information. | 07-02-2009 |
| 20090171578 | NAVIGATION SYSTEM AND METHOD FOR PROVIDING TURN-BY-TURN INSTRUCTIONS - A navigation system and method for providing turn-by-turn instructions for guiding a user along a route. The navigation system includes a global positioning system (GPS) receiving module for determining position information of the navigation system, a display unit for displaying information to guide a user along a route, a storage unit for storing map information, and a controller for processing the position information and the map information in order to concurrently provide a next turn-by-turn instruction and one or more subsequent turn-by-turn instructions to the user via the display unit. | 07-02-2009 |
| 20100138866 | METHOD FOR OUTPUTTING CONTENT INFORMATION AND DISPLAY SYSTEM ENABLING THE METHOD - A method for outputting content information and a display apparatus enabling the same are disclosed. The method for outputting contents information of a display apparatus includes identifying whether predetermined contents are series or single, generating a content information display object according to the result of the identification, and outputting the content information display object in a display screen, wherein a content information display object corresponding to the series contents is different from a content information display object corresponding to the single contents. | 06-03-2010 |
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| 20080280390 | METHOD OF FABRICATING SEMICONDUCTOR MEMORY DEVICE HAVING SELF-ALIGNED ELECTRODE, RELATED DEVICE AND ELECTRONIC SYSTEM HAVING THE SAME - A method of fabricating a semiconductor memory device having a self-aligned electrode is provided. An interlayer insulating layer having a contact hole is formed on a substrate. A phase change pattern partially filling the contact hole is formed. A bit line which includes a bit extension self-aligned to the phase change pattern and crosses over the interlayer insulating layer is formed. The bit extension may extend in the contact hole on the phase change pattern. The bit extension contacts the phase change pattern. | 11-13-2008 |
| 20090026439 | Phase Change Memory Cells Having a Cell Diode and a Bottom Electrode Self-Aligned with Each Other - Integrated circuit devices are provide having a vertical diode therein. The devices include an integrated circuit substrate and an insulating layer on the integrated circuit substrate. A contact hole penetrates the insulating layer. A vertical diode is in lower region of the contact hole and a bottom electrode in the contact hole has a bottom surface on a top surface of the vertical diode. The bottom electrode is self-aligned with the vertical diode. A top surface area of the bottom electrode is less than a horizontal section area of the contact hole. Methods of forming the integrated circuit devices and phase change memory cells are also provided. | 01-29-2009 |
| 20090166600 | INTEGRATED CIRCUIT DEVICES HAVING A STRESS BUFFER SPACER AND METHODS OF FABRICATING THE SAME - Integrated circuit devices include an integrated circuit substrate and an insulating layer on the integrated circuit substrate. A contact hole penetrates the insulating layer. A vertical diode is in the contact hole and a stress buffer spacer is provided between the vertical diode and the insulating layer. Methods of forming the integrated circuit devices are also provided. | 07-02-2009 |
| 20090230376 | RESISTIVE MEMORY DEVICES - Provided is a resistive memory device that can be integrated with a high integration density and method of forming the same. In an embodiment, a bit line is formed of copper using a damascene technique, and when the copper bit line, a copper stud may be formed around the copper bit line | 09-17-2009 |
| 20090302297 | PHASE CHANGE MEMORY DEVICES AND THEIR METHODS OF FABRICATION - In an embodiment, a phase change memory device includes a semiconductor substrate of a first conductivity type and a first interlayer insulating layer disposed on the semiconductor substrate. A hole penetrates the first interlayer insulating layer. A first and a second semiconductor pattern are sequentially stacked in a lower region of the hole. A cell electrode is provided on the second semiconductor pattern. The cell electrode has a lower surface than a top surface of the first interlayer insulating layer. A confined phase change material pattern fills the hole on the cell electrode. An upper electrode is disposed on the phase change material pattern. The phase change material pattern in the hole is self-aligned with the first and second semiconductor patterns by the hole. A method of fabricating the phase change memory device is also provided. | 12-10-2009 |
| 20100044667 | SEMICONDUCTOR DEVICES HAVING A PLANARIZED INSULATING LAYER - A semiconductor device includes at least one phase-change pattern disposed on a semiconductor substrate. A planarized capping layer, a planarized protecting layer, and a planarized insulating layer are sequentially stacked to surround sidewalls of the at least one phase-change pattern. An interconnection layer pattern is disposed on the planarized capping layer, the planarized protecting layer, and the planarized insulating layer. The interconnection layer pattern is in contact with the phase-change pattern. | 02-25-2010 |
| 20100108971 | Methods of Forming Integrated Circuit Devices Having Vertical Semiconductor Interconnects and Diodes Therein and Devices Formed Thereby - Methods of forming integrated circuit devices include forming an etch stop layer on a surface of a semiconductor substrate and forming a first interlayer insulating layer on the etch stop layer. The first interlayer insulating layer is patterned to define an opening therein that exposes a first portion of the etch stop layer. This first portion of the etch stop layer is then removed to thereby expose an underlying portion of the surface of the semiconductor substrate. This removal of the etch stop layer may be performed by wet etching the first portion of the etch stop layer using a phosphoric acid solution. A semiconductor region is then selectively grown into the opening, using the exposed portion of the surface of the semiconductor substrate as an epitaxial seed layer. | 05-06-2010 |
| 20120009755 | Semiconductor Device and Method of Fabricating the Same - A semiconductor device such as a phase change memory device includes a semiconductor substrate including an active region, a conductive pattern disposed to expose the active region, an interlayer dielectric pattern provided on the conductive pattern and including an opening formed on the exposed active region and a contact hole spaced apart from the opening to expose the conductive pattern, a semiconductor pattern and a heater electrode pattern electrically connected to the exposed active region and provided in the opening, a contact plug connected to the exposed conductive pattern and provided to fill the contact hole, and a phase change material layer provided on the heater electrode pattern. | 01-12-2012 |
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| 20090121787 | Harmonic quadrature demodulation apparatus and method thereof - Disclosed herein is a harmonic quadrature demodulation apparatus and method. The harmonic quadrature demodulation apparatus includes an input terminal for externally receiving an input focused signal, a harmonic phase estimation unit for estimating a second-order harmonic phase component from the input focused signal, and a harmonic detection unit for detecting a second-order harmonic component from the input focused signal. The second-order harmonic detection unit includes an in-phase component extractor, a quadrature component extractor, a Hilbert transformer, an adder and a low pass filter. The in-phase component extractor extracts an in-phase component of the input focused signal. The quadrature component extractor extracts a quadrature component of the input focused signal. The Hilbert transformer Hilbert-transforms a signal transmitted from the quadrature component extractor. The adder receives an output signal of the in-phase component extractor and an output signal of the Hilbert transformer, and adds the two received signals to each other. The harmonic detection unit outputs the second-order harmonic component of the input focused signal. The present invention can extract the harmonic components of an input signal through a single transmission/reception procedure without limiting the bandwidth of a transmission signal. | 05-14-2009 |
| 20090124203 | Apparatus and method for extracting second harmonic signal - Disclosed herein is an apparatus and method for extracting a second harmonic signal. The apparatus removes a fundamental frequency signal from a reception signal and then extracting the second harmonic signal. A transmitter generates a transmission signal by modulating a reference signal, and then transmits the transmission signal. A receiver extracts the second harmonic components of the reception signal by demodulating the reception signal received after the transmission signal is reflected by an external media. The transmitter includes a reference signal input unit, a first phase modulation unit, a second phase modulation unit, and a transmission signal output unit. The receiver includes a reception signal input unit, a first output signal generation unit, a second output signal generation unit, and a signal output unit. | 05-14-2009 |
