| Patent application number | Description | Published |
|---|
| 20080282229 | Apparatus and method of detecting errors in embedded software - A method and apparatus for detecting errors in an application software of an embedded system are provided. The method of detecting errors in an application software includes determining a development language of the application software and an operating system on which the application software is executed; replacing an error detection syntax inserted in order to examine an error in a predetermined function of the application software, with an error detection syntax according to the result of the determination; and performing exception handling for an error occurring in the function according to the result of the replacement, and logging error information according to the exception handling. According to the method and apparatus, an error can be automatically detected and logged irrespective of a development language and an operating system. | 11-13-2008 |
| 20090106776 | Apparatus and method for managing events in virtual world - Provided is an apparatus for managing events in a virtual world. The apparatus includes: an event detecting unit monitoring a virtual world and detecting an event which occurs in the virtual world; a snapshot managing unit generating snapshots of developments of the event; and a control unit providing each of the generated snapshots in real time. | 04-23-2009 |
| 20090150633 | Apparatus for managing memory in real-time embedded system and method of allocating, deallocating and managing memory in real-time embedded system - An apparatus for managing memory in a real-time embedded system and a method of allocating, deallocating and managing memory in a real-time embedded system. The apparatus includes a defragmentation unit performing a defragmentation task according to a predetermined priority to collect together memory fragments, and a memory manager allocating or deallocating a predetermined area of memory upon request of a task, and calculating a memory fragmentation rate of the memory to determine a priority of the defragmentation task. The method of managing memory in a real-time embedded system includes determining whether the conditions under which the memory is used vary, and if the condition vary, calculating a memory fragmentation rate of the memory to determine a priority of the defragmentation task according to the memory fragmentation rate. | 06-11-2009 |
| 20090282188 | MEMORY DEVICE AND CONTROL METHOD - A memory device includes a first controller and a second controller. The first controller receives a first command from a host and stores the first command in a first command queue, and transmits the first command to the second controller relating to the first command stored in the first command queue. The second controller transmits the first command stored in the second command queue to a flash memory. | 11-12-2009 |
| 20100088467 | MEMORY DEVICE AND OPERATING METHOD OF MEMORY DEVICE - A memory device may include a non-volatile memory and non-volatile RAM. The non-volatile memory may include a data block and a metadata block. Metadata information with respect to the data block may be included in the metadata block. A portion of metadata with respect to the data block or the metadata with respect to the metadata block may be stored in the non-volatile RAM. | 04-08-2010 |
| 20100131736 | MEMORY DEVICE AND METHOD OF OPERATION - A memory device includes a data block storing first data, and a log block storing second data that is an updated value of the first data. A spare area of the log block stores a first mapping table including mapping information between the first data and the second data. | 05-27-2010 |
| 20100146163 | MEMORY DEVICE AND MANAGEMENT METHOD OF MEMORY DEVICE - A memory device and a method of managing a memory are provided. The memory device includes a command queue configured to receive a first command from a host to store the first command, and to read and transmit the first command, a controller configured to read, from a storage device, data corresponding to the first command transmitted from the command queue, and to store the data in a buffer memory, and a first memory configured to store a data list of data stored in the buffer memory, wherein, in response to the command queue receiving the first command from the host, the controller updates the data list of data stored in the first memory. | 06-10-2010 |
| 20100199023 | APPARATUS AND METHOD FOR MANAGING MEMORY - A memory management method and apparatus are disclosed. The memory management apparatus may compute a remaining storage capacity of a flash memory based on a number of bad blocks in a flash memory or a number of block-erases of each of a plurality of blocks, and may display the computed remaining storage capacity of the flash memory. | 08-05-2010 |
| 20100235566 | FLASH MEMORY APPARATUS AND METHOD OF CONTROLLING THE SAME - Described herein is a flash memory apparatus and method controlling the same. The flash memory apparatus includes a processor and one or more flash memory units. The processor controls one or more memory operations performed in the one or more flash memory units. The processor stops controlling a memory operation in a flash memory unit when the memory operation is performed, and continues performing the memory operation in the flash memory unit when the flash memory unit generates an interrupt signal. | 09-16-2010 |
| 20100241792 | STORAGE DEVICE AND METHOD OF MANAGING A BUFFER MEMORY OF THE STORAGE DEVICE - A storage device including a processor to transmit N pages of data from one or more pages in a buffer memory where N is a natural number. The storage device also includes a flash memory to program in parallel the N pages of data to N flash chips. The N pages may be transmitted via one or more channels. | 09-23-2010 |
| 20100312977 | Method of managing memory in multiprocessor system on chip - Provided is a method of managing memory in a multiprocessor system on chip (MPSoC). According to an aspect of the present invention, locality of memory can be reflected and restricted memory resources can be efficiently used by determining a storage location of a variable or a function which corresponds to a symbol with reference to a symbol table based on memory access frequency of the variable or the function, comparing the determined storage location and a previous storage location, and copying the variable or the function stored in the previous storage location to the determined storage location if the determined storage location is different from the previous storage location. | 12-09-2010 |
| 20110016285 | Apparatus and method for scratch pad memory management - Disclosed is a scratch pad memory management device and a method thereof. The scratch pad memory management device divides a scratch pad memory into a plurality of unit blocks, maintains a memory allocation table corresponding to indices of the plurality of unit blocks in a main memory, and manages the scratch pad memory. | 01-20-2011 |
| 20110119457 | Computing system and method controlling memory of computing system - Provided is a computing system and method. The computing system may back up, based on an overlay scheme, a task of an internal memory in an external memory, and the task may be restored to the internal memory from the external memory. The computing system may include a first memory to store data associated with a first task processed in a processor, as a first data structure, a second memory to store backup data of the data associated with the first task, and a memory controller to copy, to the second memory, data other than data previously backed up in the second memory among the data associated with the first task, when the data associated with the first task is backed up in the second memory to process a second task in the processor. | 05-19-2011 |
| 20110119463 | COMPUTING SYSTEM AND METHOD CONTROLLING MEMORY OF COMPUTING SYSTEM - Provided is a computing system having a hierarchical memory structure. When a data structure is allocated with respect to a task processed in the computing system, the data structure is divided and a portion of the data structure is allocated to a high speed memory of the hierarchical memory structure and a remaining data structure is allocated to a low speed memory of the hierarchical memory. | 05-19-2011 |
| 20110119656 | Computing system, method and computer-readable medium processing debug information in computing system - Disclosed are a system, method and computer-readable medium related to processing debug information from an embedded system. Source code of an application program to be used in an embedded system may be compiled by a computing system. The application program may include a debug code line. A minimum amount of debug information is stored in an embedded system, reducing memory overhead and waste of clock cycles of a processor. | 05-19-2011 |
