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Jae Chang

Jae Chang Jung, Seoul KR

Patent application numberDescriptionPublished
20090042140ANTI-REFLECTIVE POLYMER, ANTI-REFLECTIVE COMPOSITION CONTAINING THE SAME, AND METHOD FOR FORMING PATTERN USING THE SAME - A polymer for crosslinking an anti-reflective film has a high refractive index. An anti-reflective composition containing the polymer for crosslinking is useful in an immersion lithography process using ArF (193 nm) of a semiconductor device manufacturing process.02-12-2009
20090042141ANTI-REFLECTIVE POLYMER, ANTI-REFLECTIVE COMPOSITION CONTAINING THE SAME, AND METHOD FOR FORMING PATTERN USING THE SAME - A polymer for crosslinking an anti-reflective film has a high refractive index. An anti-reflective composition containing the polymer is useful in a damascene process and an immersion lithography process using ArF (193 nm) of a semiconductor device manufacturing process.02-12-2009
20090191709Method for Manufacturing a Semiconductor Device - A polymer for immersion lithography comprising a repeating unit represented by Formula 1 and a photoresist composition containing the same. A photoresist film formed by the photoresist composition of the invention is highly resistant to dissolution, a photoacid generator in an aqueous solution for immersion lithography, thereby preventing contamination of an exposure lens and deformation of the photoresist pattern by exposure.07-30-2009
20090258498Method for Manufacturing a Semiconductor Device - A method for manufacturing a semiconductor device using a photoresist polymer comprising a fluorine component, a photoresist composition containing the photoresist polymer and an organic solvent to reduce surface tension, by forming a photoresist film uniformly on the whole surface of an underlying layer pattern to allow a subsequent ion-implanting process to be stably performed.10-15-2009
20090298291METHOD FOR FORMING A PATTERN OF A SEMICONDUCTOR DEVICE - In a method for forming a pattern of a semiconductor device, an ultra fine pattern is formed using a spacer patterning technology to overcome resolution limits of an exposer. A silicon-containing resist enhancement lithography assisted by a chemical shrink (RELACS) layer is formed with a spin-con-coating method in a track apparatus over a photoresist pattern. As a result, a cross-linking reaction is generated between the RELACS layer and the photoresist patterns to form the spacer, and the spacer is used as a mask in the patterning process.12-03-2009
20100173249Method for Manufacturing a Semiconductor Device - Disclosed herein is a composition for removing an immersion lithography solution. The composition includes an organic solvent and an acid compound. Also disclosed is a method for manufacturing a semiconductor device including an immersion lithography process. When a photoresist pattern is formed by the immersion lithography process, an exposure process is performed on a photoresist film formed over an underlying layer with an immersion lithography exposer. Then, the composition is dripped over the wafer to remove residual immersion lithography solution on the photoresist film, thereby improving a water mark defect phenomenon.07-08-2010
20100176492Method for Forming a Pattern on a Semiconductor Using an Organic Hard Mask - A composition for the organic hard mask includes a polyamic acid compound, and a method for forming a pattern is used in a manufacturing process of semiconductor devices by coating the composition for organic hard mask film on an underlying layer, and depositing a second hard mask film with a silicon nitride SiON film thereon to form a double hard mask film having an excellent etching selectivity, thereby obtaining a uniform pattern.07-15-2010

Patent applications by Jae Chang Jung, Seoul KR

Jae Chang Kim, Changwon-Si KR

Patent application numberDescriptionPublished
20090194867INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTERNAL STACKING MODULE ADHESIVE - An integrated circuit package system comprising: providing a substrate; forming a base assembled package over the substrate; forming a top package over the base assemble package; and applying a top package stacking material for stand-off or insulation to the base assembled package and the top package.08-06-2009

Jae Chang Kwon, Chilgok-Gun KR

Patent application numberDescriptionPublished
20100207122Thin film transistor array substrate and manufacturing method thereof - A thin film transistor array substrate is disclosed. The thin film transistor array substrate includes: gate lines and data lines formed to cross each other in the center of a gate insulation film on a substrate and to define pixel regions; a thin film transistor formed at each intersection of the gate and data lines; a passivation film formed on the thin film transistors; a pixel electrode formed on each of the pixel regions and connected to the thin film transistor through the passivation film; a gate pad connected to each of the gate lines through a gate linker; and a data pad connected to each of the data lines through a data linker. The data pad is formed of a gate pattern, and the data line is formed of a data pattern. The data linker is configured to connect the data pad formed of the gate pattern with the data line formed of the data pattern using a connection wiring. Also, the data linker includes the gate pattern connected to the data pad, the data pattern formed opposite to the gate pattern in the center of the gate insulation film, and the connection wiring configured to connect the gate pattern with the data pattern through a first contact hole which exposes the data pattern and the gate pattern by penetrating through the passivation film and the gate insulation film.08-19-2010