| Patent application number | Description | Published |
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| 20110085405 | SEMICONDUCTOR MEMORY DEVICE HAVING ADVANCED TAG BLOCK - A semiconductor memory device includes a row decoding block for decoding an inputted address to thereby generate a logical unit cell block address and a decoded word line address; a tag block for converting the logical unit cell block address into a physical unit cell block address; a decoded address latching block for latching the decoded word line address to thereby output the decoded word line address as a word line activation signal in response to the physical unit cell block; and a cell area for outputting a data, which is stored therein, in response to the word line activation signal. | 04-14-2011 |
| 20110169542 | DELAY CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS AND METHOD FOR DELAYING - A delay circuit of a semiconductor memory apparatus includes a decoding unit configured to decode a plurality of test signals and enable one of a plurality of control signals; a bias voltage generation unit configured to generate a first bias voltage and a second bias voltage depending upon the control signal enabled among the plurality of control signals; and a delay unit configured to determine a delay time depending upon levels of the first and second bias voltages, delay an input signal by the determined delay time, and output a resultant signal as an output signal. | 07-14-2011 |
| 20110204950 | DELAY CIRCUIT AND METHOD FOR DELAYING SIGNAL - A delay circuit includes: a delay unit configured to receive a clock signal, delay an input signal sequentially by a predetermined time interval, and output a plurality of first delayed signals; and an option unit configured to select one of the plurality of first delayed signals based on one or more select signals, and output a second delayed signal. | 08-25-2011 |
| 20110210780 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes: a plurality of chips configured to receive an external voltage. Each one of the chips detects a signal delay characteristic of the one of the chips to generate an internal voltage having a level corresponding to the signal delay characteristic. | 09-01-2011 |
| 20110211405 | EXTERNAL SIGNAL INPUT CIRCUIT OF SEMICONDUCTOR MEMORY - In one embodiment, an external signal input circuit of a semiconductor memory may include: an input block configured to receive a plurality of external signals and to generate a plurality of internal signals; and a control block configured to output one or more internal signals of the plurality of internal signals that correspond to a rank configuration of the semiconductor memory and to block output of one or more internal signals of the plurality of internal signals that do not correspond to the rank configuration. | 09-01-2011 |
| 20110211406 | ADDRESS DELAY CIRCUIT - An address delay circuit of a semiconductor memory apparatus includes a control clock delay block configured to receive a clock as a first control clock in response to a first input control signal, and output external address as the first delayed address; a control clock input selecting delay block configured to receive the clock as a second control clock in response to a second input control signal, select whether to receive the external address or the first delayed address in response to the first input control signal, and output the selected address as the second delayed address; and a control clock input/output selecting delay block configured to receive the clock, select whether to receive the external address or the second delayed address in response to the second input control signal, and output the selected address as an internal address. | 09-01-2011 |
| 20110241763 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes an individual chip designating code setting block configured to generate a plurality of individual chip designating codes which have different code values or at least two of which have the same code value, in response to a plurality of chip fuse signals; and an individual chip activation block configured to compare the plurality of individual chip designating codes with chip selection address in response to the plurality of chip fuse signals, and enable one of a plurality of individual chip activation signals based on a result of the comparison. | 10-06-2011 |
| 20110242911 | COLUMN COMMAND BUFFER AND LATENCY CIRCUIT INCLUDING THE SAME - A column command buffer includes a variable delay section configured to determine a delay time based on a frequency of a clock, and output a column command after delaying it by the delay time; and a buffering section configured to receive an output of the variable delay section and generate internal column commands. | 10-06-2011 |
| 20110242928 | ADDRESS DELAY CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS - An address delay circuit of a semiconductor memory apparatus includes a control pulse generation unit configured to generate a control pulse following a time corresponding to a predetermined multiple of cycles of a clock after a read write pulse is inputted; and a delay unit configured to output internal addresses when the control pulse is inputted, wherein the internal addresses are input as external addresses. | 10-06-2011 |
| 20110246104 | SEMICONDUCTOR APPARATUS AND CHIP SELECTING METHOD THEREOF - A semiconductor apparatus includes an individual chip designating code setting block configured to generate a plurality of individual chip designating code of different values; an individual chip activation block configured to enable an individual chip activation signal among a plurality of individual chip activation signals, which corresponds to individual chip designating code, when the individual chip designating code matches the individual chip control code; and a control block configured to set the individual chip control code or output chip selection address as the individual chip control code in response to chip selection fuse signals and test fuse signals. | 10-06-2011 |
| 20110286287 | SEMICONDUCTOR MEMORY DEVICE WITH OPTIMUM REFRESH CYCLE ACCORDING TO TEMPERATURE VARIATION - Methods for generating a refresh signal in a semiconductor device and methods for performing a refresh operation in a semiconductor memory device are disclosed. A method for generating a refresh signal includes measuring a temperature of the semiconductor memory device, generating a temperature controlled voltage based on the measured temperature, generating an N-bit digital signal based on the temperature controlled voltage, and generating a refresh signal whose frequency is determined by the N-bit digital signal. The generation of the temperature controlled voltage includes generating a first current that is increased when the measured temperature is decreased and is decreased with the measured temperature is increased, and generating the temperature controlled voltage. | 11-24-2011 |
| 20120127809 | PRECHARGE SIGNAL GENERATION CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS - A precharge signal generation circuit of a semiconductor memory apparatus may comprise a read/write precharge command generation section configured to delay a precharge command by a first delay time set in response to a control signal to generate one of a read precharge command and a write precharge command; and a read/write bank precharge address generation section configured to delay a bank column address strobe signal by a second delay time set in response to the precharge command delayed in the read/write precharge command generation section, and generate one of a read bank precharge address and a write bank precharge address. | 05-24-2012 |
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| 20100263655 | BURNER AND COOKING DEVICE - A cooking device is provided. The cooking device includes a cavity and a burner. The cavity provides a cooking chamber. The burner is in the cavity and heats food in the cooking chamber. The burner includes a supply part and a combustion part. The supply part supplies a gaseous fuel mixed with air. The combustion part burns the mixed gaseous fuel and has an open curve shape. | 10-21-2010 |
| 20100263656 | BURNER AND COOKING DEVICE - A cooking device is provided. The cooking device includes a cavity and a burner. The cavity provides a cooking chamber. The burner is at the cooking chamber in the cavity and heats food in the cooking chamber. The burner includes a supply part and a combustion unit. A gaseous fuel mixed with air flows in the supply part. The combustion unit is connected to the supply part to receive the mixed gaseous fuel and to burn the received mixed gaseous fuel flowing within the combustion unit. The combustion unit has a single loop shape. | 10-21-2010 |
| 20100263657 | GAS COOKER - A gas cooker is provided. First and second front burners are disposed on the left and the right of a front upper surface of a top plate at an interval in a row. Lower ignition parts of the first and second front burners are disposed at a distance from an imaginary straight line passing through central points of the first and second front burners in parallel with the front end of the top plate, toward a front end of the top plate. | 10-21-2010 |
| 20100263658 | GAS COOKER - Provided is a gas cooker. When foods are cooked using a top burner, inclinations of main flame holes defined in the top burner are different according to positions of the main flame holes to prevent textile disposed adjacent to a front end of a top plate from burning. Thus, a user may further safely cook the foods. | 10-21-2010 |
| 20110011389 | TOP-BURNER AND COOKER COMPRISING THE SAME - The present invention relates to a top burner and a cooker including the top burner. The present invention includes: an outer burner installed on a top surface of a top plate, and provided with a plurality of flame holes to form flames through combusting gas mixture at a perimeter thereof; an inner burner installed on a top surface of the outer burner, and provided with a plurality of flame holes to form flames through combusting gas mixture at a perimeter thereof disposed inward to the perimeter of the outer burner; a plurality of first mixing tubes supplying gas mixture mixed with air inside the outer burner; a second mixing tube supplying gas mixture mixed with air inside the inner burner; and a passage formed through the outer tube, and in which air supplied to combust gas mixture at the flame holes of the inner burner flows. Thus, according to the present invention, the advantages of heating food more efficiently while reducing incomplete combustion of gas mixture can be realized. | 01-20-2011 |
| 20110120444 | TOP-BURNER AND COOKER COMPRISING THE SAME - A top burner and a cooker having the top burner are provided. A flame transfer slit for guiding the flame formed by the combustion of the mixed gas at an outer burner to an inner burner. A shielding member is provided to shield the flame transfer slit. Therefore, the object to be heated is uniformly heated and the flame transfer from the outer burner to the inner burner can be effectively realized. | 05-26-2011 |
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| 20090002754 | IMAGE FORMING APPARATUS MANAGEMENT SERVER, SERVICE CONTINUITY SCORE (SCS) CALCULATING METHOD OF MANAGEMENT SERVER, AND IMAGE FORMING APPARATUS MANAGEMENT SYSTEM - An image forming apparatus management server, a Service Continuity Score (SCS) calculating method of the management server, and an image forming apparatus management system. A setup manager sets a priority with respect to items required to calculate an SCS indicative of a normal operation time of an image forming apparatus, an incident manager registers and manages an incident related to the image forming apparatus, and an SCS manager calculates the SCS using the registered incident and the priority set for the items. | 01-01-2009 |
| 20100006851 | Thin film transistor and method of manufacturing the same - A thin film transistor comprises a substrate; a semiconductor layer disposed on the substrate, the semiconductor layer having a source region, a drain region, and a channel region between the source region and the drain region; a gate insulating layer disposed on the semiconductor layer and on the substrate; a gate electrode disposed on the insulating layer over the channel region; an passivation layer disposed on the gate electrode and the gate insulating layer; a source electrode disposed in contact with upper, lower and side surfaces of the source region via a first contact hole through passivation layer, the gate insulating layer and the semiconductor layer; and a drain electrode disposed in contact with upper, lower and side surfaces of the drain region via a second contact hole through the passivation layer, the gate insulating layer and the semiconductor layer. | 01-14-2010 |
| 20100006852 | Thin film transistor and method of fabricating the same - A thin film transistor includes a substrate; a semiconductor layer disposed on the substrate, the semiconductor layer having a source region, a drain region, and a channel region between the source region and the drain region; a gate insulating layer disposed on the semiconductor layer and on the substrate; and a gate electrode disposed on the insulating layer over the channel region, wherein the semiconductor layer includes tapered edge portions with a taper angle defined between the tapered edge portions and a surface of the substrate is less than about 30 degrees. | 01-14-2010 |
| 20110129968 | THIN FILM TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A thin film transistor comprises a substrate; a semiconductor layer disposed on the substrate, the semiconductor layer having a source region, a drain region, and a channel region between the source region and the drain region; a gate insulating layer disposed on the semiconductor layer and on the substrate; a gate electrode disposed on the insulating layer over the channel region; an passivation layer disposed on the gate electrode and the gate insulating layer; a source electrode disposed in contact with upper, lower and side surfaces of the source region via a first contact hole through passivation layer, the gate insulating layer and the semiconductor layer; and a drain electrode disposed in contact with upper, lower and side surfaces of the drain region via a second contact hole through the passivation layer, the gate insulating layer and the semiconductor layer. | 06-02-2011 |
| 20110198604 | FILM TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A method for fabricating a thin film transistor and a thin film transistor includes a polycrystalline silicon layer formed by irradiating an amorphous silicon layer with a laser beam through an organic layer formed on the amorphous silicon layer and removing the organic layer. | 08-18-2011 |
