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| 20100211191 | Pulsed Electrical Remote Control Interface, Equipment and Satellite Comprising Such an Interface - A pulsed electrical remote control interface for an equipment item including a plurality of functions to be controlled includes at least a first command input associated with a first command line (TC-Type, TC-Type-plus, TC-Type-minus) for selecting at least one function (RF ON, RF OFF, ALC ON, ALC OFF, FCA UP, FCA DOWN, GCA UP, GCA DOWN, SCA UP, SCA DOWN, INHIBIT) to be performed from the plurality of functions and at least one second command input associated with a second command line (EXE, EXE-UP-ON, EXE-DOWN-OFF) for executing the selected function, each command input being associated with an outbound pulsed command line and a return line, the return line possibly being shared with a number of outbound lines. Applicable to the control of any kind of equipment that includes a large number of functions and requires a large number of pulsed command signals, notably in the field of satellite communication systems. | 08-19-2010 |
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| 20080206210 | Drugs for the Prevention or Treatment of Immunodeficiencies, Autoimmune Diseases or for the Induction of Immune Tolerance - The invention relates to the use of viral vectors able to stably integrate into the genome of thymic stromal cells, or of intrathymic lymphocytes or lymphocytes precursors, for the manufacture of a medicine intended for intrathymic administration in the frame of the prevention or treatment of genetic immunodeficiencies, acquired immunodeficiencies, or for the induction of immune tolerance of the organism to self or non-self gene products, cells or tissues, or for the prevention or treatment of autoimmune diseases. | 08-28-2008 |
| 20110150936 | ANTI-TUMORAL CELLS - The present invention relates to the field of preventive or therapeutic anti-tumoral vaccine. More specifically, the present invention relates to live animal tumour cells having a negative MHC-I phenotype, to methods for the production of such MHC-I negative cells, and to their therapeutic use as anti-tumoral agents, particularly via their capacity to activate natural killer (NK) cells. The invention further relates to methods for modulating the level of expression of MHC-I molecules on animal tumour cells, for example by use of specific culture conditions, and/or by use of exogenous agents which directly or indirectly affect levels of MHC-I expression. The invention also concerns activated NK cells and their therapeutic use as anti-tumoral agents. | 06-23-2011 |
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| 20110097909 | INTERCONNECT STRUCTURE WITH CAVITY HAVING ONE OR SEVERAL CONTACT RISES ON THE WALL OF THE CAVITY AND METHOD FOR PRODUCING SAME - The invention concerns an interconnect device comprising a support ( | 04-28-2011 |
| 20110219612 | METHOD FOR METALIZING BLIND VIAS - A method for metalizing at least one blind via formed in at least one substrate, including at least the following steps:
| 09-15-2011 |
| 20120006783 | METHOD FOR PRODUCING A DEVICE WITH A FLUID-ENCAPSULATING MEMBRANE - The invention relates to a method for producing a device with a membrane used to encapsulate a fluid contained in a cavity, in which:
| 01-12-2012 |
| 20120031874 | METHOD FOR MAKING A CAVITY IN THE THICKNESS OF A SUBSTRATE WHICH MAY FORM A SITE FOR RECEIVING A COMPONENT - A method for making a micro-device including at least one receiving site for components, formed in a thickness of a substrate. The method includes: a) making in at least one first substrate adhesively bonded to a second substrate via a discontinuous adhesive bonding interface, at least one first trench around at least one sacrificial block of the first substrate, by etching the first substrate so as to expose the adhesive bonding interface; and b) removing the sacrificial block so as to make at least one first cavity in the first substrate. | 02-09-2012 |
| 20120112293 | SEALED CAVITY AND METHOD FOR PRODUCING SUCH A SEALED CAVITY - A method for producing a sealed cavity, including: a) producing a sacrificial layer on a substrate; b) producing a cover layer covering at least the sacrificial layer and a portion of the face of the substrate not covered by the sacrificial layer, the cover layer including lateral flanks forming, with the substrate, an angle of less than 90°; c) producing a hole through one of the lateral flanks of the cover layer such that a maximum distance between the substrate and an edge of the hole is less than approximately 3 μm, the hole crossing a portion of the cover layer deposited on a portion of the substrate not covered by the sacrificial layer; d) eliminating the sacrificial layer through the hole, forming the cavity; and e) depositing at least one material plugging the hole in a sealed fashion. | 05-10-2012 |
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| 20080198678 | PROGRAMMABLE SRAM SOURCE BIAS SCHEME FOR USE WITH SWITCHABLE SRAM POWER SUPPLY SETS OF VOLTAGES - A memory circuit has a high voltage and low voltage supply nodes. One of a first and second sets of voltages is selectively applied to the supply nodes of the memory circuit in dependence upon memory operational mode. If in active read/write mode, then the first set of voltages is selectively applied. Conversely, if in standby no-read/no-write mode, then the second set of voltages is selectively applied. A low voltage in the second set of voltages is greater than a low voltage in the first set of voltages by a selected one of a plurality of low offset voltages, and a high voltage in the second set of voltages is less than a high voltage in the first set of voltages by a selected one of a plurality of high offset voltages. The offset voltages are provided by diode-based circuits that are selectively active. Selective activation is provided by either selectably blowable fuse elements or selectively activated switching elements. | 08-21-2008 |
| 20080198679 | SRAM WITH SWITCHABLE POWER SUPPLY SETS OF VOLTAGES - A circuit includes a memory cell having a high voltage supply node and a low voltage supply node. Power multiplexing circuitry is provided to selectively apply one of a first set of voltages and a second set of voltages to the high and low voltage supply nodes of the cell in dependence upon a current operational mode of the cell. If the cell is in active read or write mode, then the multiplexing circuitry selectively applies the first set of voltages to the high and low voltage supply nodes. Conversely, if the cell is in standby no-read or no-write mode, then the multiplexing circuitry selectively applies the second set of voltages to the high and low voltage supply nodes. The second set of voltages are offset from the first set of voltages. More particularly, a low voltage in the second set of voltages is higher than a low voltage in the first set of voltages, and wherein a high voltage in the second set of voltages is less than a high voltage in the first set of voltages. The cell can be a member of an array of cells, in which case the selective application of voltages applies to the array depending on the active/standby mode of the array. The array can comprise a block or section within an overall memory device including many blocks or sections, in which case the selective application of voltages applies to individual blocks/sections depending on the active/standby mode of the block/section itself. | 08-21-2008 |
| 20090196085 | SRAM MEMORY CELL PROTECTED AGAINST CURRENT OR VOLTAGE SPIKES - A memory cell is protected against current or voltage spikes. The cell includes a group of redundant data storage nodes for the storage of information in at least one pair of complementary nodes. The cell further includes circuitry for restoring information to its initial state following a current or voltage spike which modifies the information in one of the nodes of the pair using the information stored in the other node. The data storage nodes of each pair in the cell are implanted on opposite sides of an opposite conductivity type well from one another within a region of a substrate defining the boundaries of the memory cell. | 08-06-2009 |
| 20100265758 | Method for implementing an SRAM memory information storage device - A device, and a corresponding method of implementation, for SRAM memory information storage are provided. The device is powered by a supply voltage and includes an array of base cells organized in base columns, and at least one mirror column of at least one mirror cell liable to simulate the behavior of the cells in a base column. The device further includes Emulation means, in a mirror column, of the most restricting cell in a base column, Means for varying a mirror power supply voltage for the mirror column, and Means for copying the mirror power supply voltage in the emulated base column. | 10-21-2010 |
| 20100312939 | INTERCONNECTION NETWORK WITH DYNAMIC SUB-NETWORKS - An interconnection network with m first electronic circuits and n second electronic circuits, comprising m interconnection sub-networks, each comprising: | 12-09-2010 |
| 20110095816 | NETWORK ON CHIP BUILDING BRICKS - The present invention relates to a Network on chip comprising a torus matrix of processing elements formed by a juxtaposition of bricks in rows and columns, each brick comprising a longitudinal extra-connection bus segment connecting two terminals situated on opposite transverse edges of the brick on a first axis; two longitudinal intra-connection bus segments connecting circuits of the brick to respective terminals situated on the opposite transverse edges on a second axis symmetrical to the first axis with respect to the center of the brick; a transverse extra-connection bus segment connecting two terminals situated on opposite longitudinal edges of the brick on a third axis; and two transverse intra-connection bus segments connecting circuits of the brick to respective terminals situated on the opposite longitudinal edges on a fourth axis symmetrical to the third axis with respect to the center of the brick. The bricks are oriented at 180° from one to the next in the direction of the columns and in the direction of the rows, and each brick comprises an even number of power supply conductor segments arranged symmetrically with respect to an axis of symmetry of the brick and connecting opposite edges of the brick. | 04-28-2011 |
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| 20080319978 | HYBRID SYSTEM FOR NAMED ENTITY RESOLUTION - A method for named entity resolution includes parsing an input text string to identify a context in which an identified named entity of the input text string is used. The identified context is compared with at least one stored context in which the named entity in the stored context is associated with a class of named entity, the named entity class being selected from a plurality of classes, at least one of the plurality of classes corresponding to a metonymic use of a respective named entity. A named entity class is assigned to the identified named entity from the plurality of named entity classes, based on at least one of the identified context and the comparison. | 12-25-2008 |
| 20100004925 | Clique based clustering for named entity recognition system - A soft clustering method comprises (i) grouping items into non-exclusive cliques based on features associated with the items, and (ii) clustering the non-exclusive cliques using a hard clustering algorithm to generate item groups on the basis of mutual similarity of the features of the items constituting the cliques. In some named entity recognition embodiments illustrated herein as examples, named entities together with contexts are grouped into cliques based on mutual context similarity. Each clique includes a plurality of different named entities having mutual context similarity. The cliques are clustered to generate named entity groups on the basis of mutual similarity of the contexts of the named entities constituting the cliques. | 01-07-2010 |
| 20110276322 | TEXTUAL ENTAILMENT METHOD FOR LINKING TEXT OF AN ABSTRACT TO TEXT IN THE MAIN BODY OF A DOCUMENT - Aspects of the exemplary embodiment relate to a system and method for processing a document which enables assessment of the coherence of an abstract of the document. The method includes storing the document in memory and, for each sentence of the abstract, comparing the sentence with sentences of a main body of the document using textual entailment techniques to identify whether the sentence of the abstract entails a sentence in the main body of the document. Links can then be generated between the entailing sentences of the abstract and the corresponding entailed sentences of the document. The document and generated links are output. The links enable the coherence of the abstract to be evaluated, either manually or automatically, using an evaluation component of the system. | 11-10-2011 |
