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Jacob B.
Jacob B. Dadson, Wappingers Falls, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20120086103 | TECHNIQUE TO CREATE A BURIED PLATE IN EMBEDDED DYNAMIC RANDOM ACCESS MEMORY DEVICE - A method for forming a trench structure is provided for a semiconductor and/or memory device, such as an DRAM device. In one embodiment, the method for forming a trench structure includes forming a trench in a semiconductor substrate, and exposing the sidewalls of the trench to an arsenic-containing gas to adsorb an arsenic containing layer on the sidewalls of the trench. A material layer is then deposited on the sidewalls of the trench to encapsulate the arsenic-containing layer between the material layer and sidewalls of the trench. | 04-12-2012 |
Jacob B. Erich, San Mateo, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110145493 | Independently Controlled Virtual Memory Devices In Memory Modules - Various embodiments of the present invention are directed a multi-core memory modules. In one embodiment, a memory module ( | 06-16-2011 |
Jacob B. Khurgin, Pikesville, MD US
| Patent application number | Description | Published |
|---|---|---|
| 20110188112 | Nonlinear Frequency Conversion in Nanoslot Optical Waveguides - A waveguide device for frequency mixing or conversion through birefringent phase matching, having two suspended horizontal waveguides with an air-filled horizontal nanoslot between them. The waveguides are formed of a material with a high nonlinear susceptibility, and one waveguide can be n-doped with the other waveguide slab being p-doped. The system can be tuned to operate at different frequencies by varying the nanoslot gap distance by electrostatically actuating the suspended air-clad waveguides. | 08-04-2011 |
Jacob B. Leverich, San Mateo, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100194470 | Integrated Circuit Package - An integrated circuit package includes a digital logic die disposed on a substrate; and an interposer die stacked vertically with the digital logic die on the substrate. The interposer die includes at least one vertical transistor configured to selectively provide electrical power to a portion of the digital logic die. | 08-05-2010 |
| 20110138387 | Dynamic Utilization of Power-Down Modes in Multi-Core Memory Modules - Various embodiments of the present invention are directed to methods that enable a memory controller to choose a particular operation mode for virtual memory devices of a memory module based on dynamic program behavior. In one embodiment, a method for determining an operation mode for each virtual memory device of a memory module includes selecting a metric ( | 06-09-2011 |