| Patent application number | Description | Published |
|---|
| 20080242117 | APPARATUS TO REDUCE WAFER EDGE TEMPERATURE AND BREAKAGE OF WAFERS - In some embodiments radiation incident on a wafer is provided to perform an annealing process, and the wafer is cooled at an edge portion to reduce temperature and stress on the wafer. Other embodiments are described and claimed. | 10-02-2008 |
| 20090020825 | Forming dual metal complementary metal oxide semiconductor integrated circuits - Complementary metal oxide semiconductor metal gate transistors may be formed by depositing a metal layer in trenches formerly inhabited by patterned gate structures. The patterned gate structures may have been formed of polysilicon in one embodiment. The metal layer may have a workfunction most suitable for forming one type of transistor, but is used to form both the n and p-type transistors. The workfunction of the metal layer may be converted, for example, by ion implantation to make it more suitable for use in forming transistors of the opposite type. | 01-22-2009 |
| 20090152601 | Strained NMOS transistor featuring deep carbon doped regions and raised donor doped source and drain - Some embodiments of the present invention include providing carbon doped regions and raised source/drain regions to provide tensile stress in NMOS transistor channels. | 06-18-2009 |
| 20090323759 | Temperature measurement with reduced extraneous infrared in a processing chamber - Temperature measurement using a pyrometer in a processing chamber is described. The extraneous light received by the pyrometer is reduced. In one example, a photodetector is used to measure the intensity of light within the processing chamber at a defined wavelength. A temperature circuit is used to convert the measured light intensity to a temperature signal, and a doped optical window between a heat source and a workpiece inside processing chamber is used to absorb light at the defined wavelength directed at the workpiece from the heat source. | 12-31-2009 |
| 20090325392 | SUB-SECOND ANNEALING PROCESSES FOR SEMICONDUCTOR DEVICES - An annealing method and apparatus for semiconductor manufacturing is described. The method and apparatus allows an anneal that can span a thermal budget and be tailored to a specific process and its corresponding activation energy. In some cases, the annealing method spans a timeframe from about 1 millisecond to about 1 second. An example for this annealing method includes a sub-second anneal method where a reduction in the formation of nickel pipes is achieved during salicide processing. In some cases, the method and apparatus combine the rapid heating rate of a sub-second anneal with a thermally conductive substrate to provide quick cooling for a silicon wafer. Thus, the thermal budget of the sub-second anneal methods may span the range from conventional RTP anneals to flash annealing processes (including duration of the anneal, as well as peak temperature). Other embodiments are described. | 12-31-2009 |
| 20110068403 | STRAINED NMOS TRANSISTOR FEATURING DEEP CARBON DOPED REGIONS AND RAISED DONOR DOPED SOURCE AND DRAIN - Some embodiments of the present invention include providing carbon doped regions and raised source/drain regions to provide tensile stress in NMOS transistor channels. | 03-24-2011 |
| 20110147804 | Drive current enhancement in tri-gate MOSFETS by introduction of compressive metal gate stress using ion implantation - A semiconductor device comprises a fin and a metal gate film. The fin is formed on a surface of a semiconductor material. The metal gate film formed on the fin and comprises ions implanted in the metal gate film to form a compressive stress within the metal gate. In one exemplary embodiment, the surface of the semiconductor material comprises a (100) crystalline lattice orientation, and an orientation of the fin is along a <100> direction with respect to the crystalline lattice of the semiconductor. In another exemplary embodiment, the surface of the semiconductor material comprises a (100) crystalline lattice orientation, and the orientation of the fin is along a <110> direction with respect to the crystalline lattice of the semiconductor. The fin comprises an out-of-plane compression that is generated by the compressive stress within the metal gate film. | 06-23-2011 |
| 20110147831 | METHOD FOR REPLACEMENT METAL GATE FILL - An exemplary embodiment of a method for forming a gate for a planar-type or a finFET-type transistor comprises forming a gate trench that includes an interior surface. A first work-function metal is formed on the interior surface of the gate trench, and a low-resistivity material is deposited on the first work-function metal using a chemical vapor deposition (CVD) technique, or an atomic layer deposition (ALD) technique, or combinations thereof. Another exemplary embodiment provides that a second work-function metal is formed on the first work-function metal, and then the low-resistivity material is deposited on the first work-function metal using a chemical vapor deposition (CVD) technique, or an atomic layer deposition (ALD) technique, or combinations thereof. | 06-23-2011 |
| 20110156107 | Self-aligned contacts - A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations. | 06-30-2011 |
