| Patent application number | Description | Published |
|---|
| 20080218290 | Automatic Driver/Transmission Line/Receiver Impedance Matching Circuitry - An impedance matcher that automatically matches impedance between a driver and a receiver. The impedance matcher includes a phase-locked loop (PLL) circuit that locks onto a data signal provided by the driver. The impedance matcher also includes tunable impedance matching circuitry responsive to one or more voltage-controlled oscillator control signals within the PLL circuit so as to generate an output signal that is impedance matched with the receiver. | 09-11-2008 |
| 20080237708 | SILICON ON INSULATOR (SOI) FIELD EFFECT TRANSISTORS (FETs) WITH ADJACENT BODY CONTACTS - A field effect transistor (FET) with an adjacent body contact, a SOI IC with circuits including the FETs and a method of fabricating the ICs. Device islands are formed in the silicon surface layer of a SOI wafer. Gates are defined on the wafer. Body contacts are formed in a perimeter conductive region adjacent to the gates. The body contacts may be either a silicide strap along the gate sidewall at one side of the FET or a separate contact separated from the gate by a dielectric stripe at one side of the FET. Separate contacts may be connected to a bias supply. | 10-02-2008 |
| 20080258857 | ELECTRONIC FUSE WITH CONFORMAL FUSE ELEMENT FORMED OVER A FREESTANDING DIELECTRIC SPACER - An electronic fuse for an integrated circuit and a method of fabrication thereof are presented. The electronic fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The fuse element has a convex upper surface and a lower surface with a radius of curvature at a smallest surface area of curvature less than or equal to 100 nanometers. Fabricating the electronic fuse includes forming an at least partially freestanding dielectric spacer above a supporting structure, and then conformably forming the fuse element of the fuse over at least a portion of the freestanding dielectric spacer, with the fuse element characterized as noted above. The dielectric spacer may remain in place as a thermally insulating layer underneath the fuse element, or may be removed to form a void underneath the fuse element. | 10-23-2008 |
| 20080283918 | Ultra Thin Channel (UTC) MOSFET Structure Formed on BOX Regions Having Different Depths and Different Thicknesses Beneath the UTC and SourceDrain Regions and Method of Manufacture Thereof - A MOSFET structure includes a planar semiconductor substrate, a gate dielectric and a gate. A UT SOI channel extends to a first depth below the top surface of the substrate and is self-aligned to and is laterally coextensive with the gate. Source-drain regions, extend to a second depth greater than the first depth below the top surface, and are self-aligned to the UT channel region. A BOX | 11-20-2008 |
| 20080289651 | METHOD AND APPARATUS FOR WAFER EDGE CLEANING - A wafer edge cleaning system that includes a wafer dry etching chamber and one or more irradiation sources preferably positioned inside the wafer dry etching chamber. The irradiation source such as laser generates a beam aimed at the periphery of the wafer to melt any defects, in particular, black silicon at the edge of the wafer. Preferably, the wafer is mounted on a rotating platform. The invention further provides a method for removing black silicon at the edge of a semiconductor wafer that includes the steps of: patterning the wafer with a trench mask layer; etching the wafer to form a trench thereon; exposing the edge of the wafer to a laser beam to melt the black silicon thereon; stripping the mask and cleaning the wafer. | 11-27-2008 |
| 20080290413 | SOI MOSFET WITH A METAL SEMICONDUCTOR ALLOY GATE-TO-BODY BRIDGE - A body contact region is formed in a portion of the active region. A gate dielectric and a gate conductor layer are formed on the active region and patterned to define a gate electrode. A portion of the gate electrode is removed to expose a top surface of the body contact region adjoining a sidewall of the gate dielectric which adjoins a sidewall of the gate conductor. A substrate metal semiconductor alloy is formed on the top surface of the body contact region, and a gate metal semiconductor alloy is formed on the sidewall of the gate conductor. The substrate metal semiconductor alloy and the gate metal semiconductor alloy are adjoined during formation, providing a gate-to-body bridge of a MOSFET formed on the active region. | 11-27-2008 |
| 20080296728 | SEMICONDUCTOR STRUCTURE FOR FUSE AND ANTI-FUSE APPLICATIONS - A fuse/anti-fuse structure is provided in which programming of the anti-fuse is caused by an electromigation induced hillock that is formed adjacent to the fuse element. The hillock ruptures a thin diffusion barrier located on the sidewalls of the fuse element and the conductive material within the fuse element diffuses into the adjacent dielectric material. The fuse element includes a conductive material located within a line opening which includes a first diffusion barrier having a first thickness located on sidewalls and a bottom wall of the line opening. The anti-fuse element includes the conductive material located within a combined via and line opening which includes the first diffusion barrier located on sidewalls and a bottom wall of the combined via and line opening and a second diffusion barrier having a second thickness that is greater than the first thickness located on the first diffusion barrier. | 12-04-2008 |
| 20090001464 | FINFET WITH TOP BODY CONTACT - FinFETs are provided with a body contact on a top surface of a semiconductor fin. The top body contact may be self-aligned with respect to the semiconductor fin and the source and drain regions. Alternately, the source and drain regions may be formed recessed from the top surface of the semiconductor fin. The body or an extension of the body may be contacted above the channel or above one of the source and drain regions. Electrical shorts between the source and drain and the body contacts are avoided by the recessing of the source and drain regions from the top surface of the semiconductor fin. | 01-01-2009 |
| 20090001481 | DIGITAL CIRCUITS HAVING ADDITIONAL CAPACITORS FOR ADDITIONAL STABILITY - A semiconductor structure and a method for forming the same. The semiconductor structure includes (a) a semiconductor substrate, (b) a shallow trench isolation (STI) region on the semiconductor substrate, and (c) a first semiconductor transistor on the semiconductor substrate. The first semiconductor transistor includes (I) a first source/drain region, (ii) a second source/drain region, and (iii) a first gate electrode region. The first and second source/drain regions are doped with a same doping polarity. The semiconductor structure further includes a first doped region in the semiconductor substrate. The first doped region is on a first side wall and a bottom wall of the STI region. The first doped region is in direct physical contact with the second source/drain region. The first doped region and the second source/drain region are doped with a same doping polarity. | 01-01-2009 |
| 20090008705 | BODY-CONTACTED FINFET - A silicon containing fin is formed on a semiconductor substrate. A silicon oxide layer is formed around the bottom of the silicon containing fin. A gate dielectric is formed on the silicon containing fin followed by formation of a gate electrode. While protecting the portion of the semiconductor fin around the channel, a bottom portion of the silicon containing semiconductor fin is etched by a isotropic etch leaving a body strap between the channel of a finFET on the silicon containing fin and an underlying semiconductor layer underneath the silicon oxide layer. The fin may comprise a stack of inhomogeneous layers in which a bottom layer is etched selectively to a top semiconductor layer. Alternatively, the fin may comprise a homogeneous semiconductor material and the silicon containing fin may be protected by dielectric films on the sidewalls and top surfaces of the silicon containing fin. | 01-08-2009 |
| 20090020827 | THIN GATE ELECTRODE CMOS DEVICES AND METHODS OF FABRICATING SAME - A CMOS device and method of forming the CMOS device. The device including a source and a drain formed in a semiconductor substrate, the source and the drain and separated by a channel region of the substrate; a gate dielectric formed on a top surface of the substrate and a very thin metal or metal alloy gate electrode formed on a top surface of the gate dielectric layer, a polysilicon line abutting and in electrical contact with the gate electrode, the polysilicon line thicker than the gate electrode. The method including, forming the gate electrode by forming a trench above the channel region and depositing metal into the trench. | 01-22-2009 |
| 20090026491 | TUNNELING EFFECT TRANSISTOR WITH SELF-ALIGNED GATE - In one embodiment, a mandrel and an outer dummy spacer may be employed to form a first conductivity type region. The mandrel is removed to form a recessed region wherein a second conductivity type region is formed. In another embodiment, a mandrel is removed from within shallow trench isolation to form a recessed region, in which an inner dummy spacer is formed. A first conductivity type region and a second conductivity region are formed within the remainder of the recessed region. An anneal is performed so that the first conductivity type region and the second conductivity type region abut each other by diffusion. A gate electrode is formed in self-alignment to the p-n junction between the first and second conductivity regions. The p-n junction controlled by the gate electrode, which may be sublithographic, constitutes an inventive tunneling effect transistor. | 01-29-2009 |
| 20090047756 | DUAL PORT GAIN CELL WITH SIDE AND TOP GATED READ TRANSISTOR - A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity. | 02-19-2009 |
| 20090072290 | SOI CMOS COMPATIBLE MULTIPLANAR CAPACITOR - An isolated shallow trench isolation portion is formed in a top semiconductor portion of a semiconductor-on-insulator substrate along with a shallow trench isolation structure. A trench in the shape of a ring is formed around a doped top semiconductor portion and filled with a conductive material such as doped polysilicon. The isolated shallow trench isolation portion and the portion of a buried insulator layer bounded by a ring of the conductive material are etched to form a cavity. A capacitor dielectric is formed on exposed semiconductor surfaces within the cavity and above the doped top semiconductor portion. A conductive material portion formed in the trench and above the doped top semiconductor portion constitutes an inner electrode of a capacitor, while the ring of the conductive material, the doped top semiconductor portion, and a portion of a handle substrate abutting the capacitor dielectric constitute a second electrode. | 03-19-2009 |
| 20090115448 | Design Structure for an Automatic Driver/Transmission Line/Receiver Impedance Matching Circuitry - A design structure for an impedance matcher that automatically matches impedance between a driver and a receiver. The design structure for an impedance matcher includes a phase-locked loop (PLL) circuit that locks onto a data signal provided by the driver. The impedance matcher also includes tunable impedance matching circuitry responsive to one or more voltage-controlled oscillator control signals within the PLL circuit so as to generate an output signal that is impedance matched with the receiver. | 05-07-2009 |
| 20090147568 | Memory Elements and Methods of Using the Same - In a first aspect, a first apparatus is provided. The first apparatus is a memory element that includes (1) one or more MOSFETs each including a dielectric material having a dielectric constant of about 3.9 to about 25; and (2) control logic coupled to at least one of the one or more MOSFETs. The control logic is adapted to (a) cause the memory element to operate in a first mode to store data; and (b) cause the memory element to operate in a second mode to change a threshold voltage of at least one of the one or more MOSFETs from an original threshold voltage to a changed threshold voltage such that the changed threshold voltage affects data stored by the memory element when operated in the first mode. Numerous other aspects are provided. | 06-11-2009 |
| 20090158226 | HIGH-DENSITY, TRENCH-BASED NON-VOLATILE RANDOM ACCESS SONOS MEMORY CELLS FOR SOC APPLICATIONS - The present invention provides two-transistor silicon-oxide-nitride-oxide-semiconductor (2-Tr SONOS) non-volatile memory cells with randomly accessible storage locations as well as a design structure including the semiconductor memory devices embodied in a machine readable medium. In one embodiment, a 2-Tr SONOS cell is provided in which the select transistor is located with a trench structure having trench depth from 1 to 2 μm and the memory transistor is located on a surface of a semiconductor substrate adjoining the trench structure. In another embodiment, a 2-Tr SONOS memory cell is provided in which both the select transistor and the memory transistor are located within a trench structure having the depth mentioned above. | 06-18-2009 |
| 20090158234 | VERTICAL SOI TRENCH SONOS CELL - A semiconductor memory device and a design structure including the semiconductor memory device embodied in a machine readable medium is provided. In particular the present invention includes a semiconductor memory device in which a vertical trench semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell is created in a semiconductor-on-insulator (SOI) substrate is provided that allows for the integration of dense non-volatile random access memory (NVRAM) cells in SOI-based complementary metal oxide semiconductor (CMOS) technology. The trench is processed using conventional trench processing and it is processed near the beginning of the inventive method that allows for the fabrication of the memory cell to be fully separated from SOI logic processing. | 06-18-2009 |
| 20090176339 | Method of multi-port memory fabrication with parallel connected trench capacitors in a cell - A method is provided for fabricating a multi-port memory in which a plurality of parallel connected capacitors are in a cell. A plurality of trench capacitors are formed which have capacitor dielectric layers extending along walls of the plurality of trenches, the plurality of trench capacitors having first capacitor plates and second capacitor plates opposite the capacitor dielectric layers from the first capacitor plates. The first capacitor plates are conductively tied together and the second capacitor plates are conductively tied together. In this way, the first capacitor plates are adapted to receive a same variable voltage and the second capacitor plates are adapted to receive a same fixed voltage. | 07-09-2009 |
| 20090212341 | SEMITUBULAR METAL-OXIDE-SEMICONDUCTOR FIELD EFFECT TRANSISTOR - An epitaxial semiconductor layer or a stack of a silicon germanium alloy layer and an epitaxial strained silicon layer is formed on outer sidewalls of a porous silicon portion on a substrate. The porous silicon portion and any silicon germanium alloy material are removed and a semitubular epitaxial semiconductor structure in a three-walled configuration is formed. A semitubular field effect transistor comprising inner and outer gate dielectric layers, an inner gate electrode, an outer gate electrode, and source and drain regions is formed on the semitubular epitaxial semiconductor structure. The semitubular field effect transistor may operate as an SOI transistor with a tighter channel control through the inner and outer gate electrodes, or as a memory device storing electrical charges in the body region within the semitubular epitaxial semiconductor structure. | 08-27-2009 |
| 20090212362 | SOI FIELD EFFECT TRANSISTOR WITH A BACK GATE FOR MODULATING A FLOATING BODY - A masking layer is applied over a top semiconductor layer and patterned to expose in an opening a shallow trench isolation structure and a portion of a top semiconductor region within which a first source/drain region and a body is to be formed. Ions are implanted into a portion of a buried insulator layer within the area of the opening to form damaged buried insulator region. The shallow trench isolation structure is removed and the damaged buried insulator region is etched selective to undamaged buried insulator portions to form a cavity. A dielectric layer is formed on the sidewalls and the exposed bottom surface of the top semiconductor region and a back gate filling the cavity is formed. A contact is formed to provide an electrical bias to the back gate so that the electrical potential of the body and the first source/drain region is electrically modulated. | 08-27-2009 |
| 20090231771 | Magnetic Induction Grid as an Early Warning Mechanism for Space Based Microelectronics - A system for protecting an electronic device from cosmic rays includes a frame in which the circuit is disposed, a cosmic ray detection circuit and a protection circuit. The cosmic ray detection circuit is supported by the frame and is spaced apart from the circuit. The cosmic ray detection circuit is configured to assert an incoming cosmic ray signal when a cosmic ray interacts with the cosmic ray detection device. The protection circuit is coupled to the incoming cosmic ray signal and is configured to cause the electronic device to enter a protected state when the cosmic ray signal is asserted. | 09-17-2009 |
| 20090244954 | STRUCTURE AND METHOD FOR IMPROVING STORAGE LATCH SUSCEPTIBILITY TO SINGLE EVENT UPSETS - A digital logic storage structure includes cross coupled first and second complementary metal oxide semiconductor (CMOS) inverters formed on a semiconductor substrate, the CMOS inverters including a first storage node and a second storage node that is the logical complement of the first storage node; both of the first and second storage nodes each selectively coupled to a deep trench capacitor through a switching transistor, with the switching transistors controlled by a common capacitance switch line coupled to gate conductors thereof; wherein, in a first mode of operation, the switching transistors are rendered nonconductive so as to isolate the deep trench capacitors from the inverter storage nodes and, in a second mode of operation, the switching transistors are rendered conductive so as to couple the deep trench capacitors to their respective storage nodes, thereby providing increased resistance of the storage nodes to single event upsets (SEUs). | 10-01-2009 |
| 20090309136 | SEA-OF-FINS STRUCTURE OF A SEMICONDUCTOR SUBSTRATE AND METHOD OF FABRICATION - A semiconductor device and a method of fabricating a semiconductor device, wherein the method comprises forming, on a substrate, a plurality of planarized fin bodies to be used for customized fin field effect transistor (FinFET) device formation; forming a nitride spacer around each of the plurality of fin bodies; forming an isolation region in between each of the fin bodies; and coating the plurality of fin bodies, the nitride spacers, and the isolation regions with a protective film. The fabricated semiconductor device is adapted to be used in customized applications as a customized semiconductor device. | 12-17-2009 |
| 20100230781 | TRENCH ANTI-FUSE STRUCTURES FOR A PROGRAMMABLE INTEGRATED CIRCUIT - Trench anti-fuse structures, design structures embodied in a machine readable medium for designing, manufacturing, or testing a programmable integrated circuit. The anti-fuse structure includes a trench having a plurality of sidewalls that extend into a substrate, a doped region in the semiconductor material of the substrate proximate to the sidewalls of the trench, a conductive plug in the trench, and a dielectric layer on the sidewalls of the trench. The dielectric layer is disposed between the conductive plug and the doped region. The dielectric layer is configured so that a programming voltage applied between the doped region and the conductive plug causes a breakdown of the dielectric layer within a region of the trench. The trench sidewalls are arranged with a cross-sectional geometrical shape that is independent of position between a bottom wall of the deep trench and a top surface of the substrate. | 09-16-2010 |
| 20110163365 | STRUCTURE AND METHOD FOR IMPROVING STORAGE LATCH SUSCEPTIBILITY TO SINGLE EVENT UPSETS - A digital logic storage structure includes cross coupled first and second complementary metal oxide semiconductor (CMOS) inverters formed on a semiconductor substrate, the CMOS inverters including a first storage node and a second storage node that is the logical complement of the first storage node; both of the first and second storage nodes each selectively coupled to a deep trench capacitor through a switching transistor, with the switching transistors controlled by a common capacitance switch line coupled to gate conductors thereof; wherein, in a first mode of operation, the switching transistors are rendered nonconductive so as to isolate the deep trench capacitors from the inverter storage nodes and, in a second mode of operation, the switching transistors are rendered conductive so as to couple the deep trench capacitors to their respective storage nodes, thereby providing increased resistance of the storage nodes to single event upsets (SEUs). | 07-07-2011 |
