# Izumi Nitta, Kawasaki JP

## Izumi Nitta, Kawasaki JP

Patent application number | Description | Published |
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20080222586 | Delay analysis apparatus, delay analysis method and computer product - Within-die delay distributions and die-to-die delay distributions of two arbitrary paths in an analysis target circuit are extracted from a delay distribution library, and an effect index indicative of a relative error of an overall path delay distribution of one path and an overall path delay distribution when the two paths are integrated as one path is calculated based on the within-die delay distributions and the die-to-die delay distributions of the two paths. When the effect index is determined to be equal to or above a threshold, the overall path delay distribution of the two paths integrated as one path is calculated. Hence, a path that affects an analysis result alone is selected to execute a statistical Max operation, thereby increasing a speed of delay analysis processing. | 09-11-2008 |

20080244487 | Delay analysis support apparatus, delay analysis support method and computer product - A delay analysis support apparatus that supports analysis of delay in a target circuit includes an acquiring unit that acquires error information concerning a cell-delay estimation error that is dependent on a characterizing tool; an error calculating unit that calculates, based on the error information and a first probability density distribution concerning the cell delay of each cell and obtained from the cell delay estimated by the characterizing tool, a second probability density distribution that concerns the cell-delay estimation error of each cell; and an linking unit that links the second probability density distribution and a cell library storing therein the first probability density distribution. | 10-02-2008 |

20090007044 | Design support method and apparatus, and computer product - A design support apparatus includes an extracting unit that extracts a first cell from among plural cells in a target circuit; a detecting unit that detects a second cell arranged adjacent to the first cell; and a setting unit that sets a delay value of the first cell according to an arrangement pattern of the second cell. | 01-01-2009 |

20090055142 | METHOD AND APPARATUS FOR ESTIMATING MAN-HOURS - A method for estimating a man-hours of an entire project having a series of tasks with a computer includes, inputting an estimated man-hours of the each task, acquiring model functions for extracting estimation errors included in the estimated man-hours of the each task based on an attribute of a worker who performs the each task, calculating a probability density distribution representing estimation errors depending on the attribute and a probability density distribution representing modeling errors depending on methods for estimating the man-hours for each task using the model functions, calculating man-hours of the entire project having a series of tasks for the each task using statistical methods to accumulate the probability density distribution representing estimation errors and the probability density distribution representing the modeling errors, and outputting calculating results of man-hours of the entire project to a output device. | 02-26-2009 |

20090138838 | METHOD AND APPARATUS FOR SUPPORTING DELAY ANALYSIS, AND COMPUTER PRODUCT - A delay distribution of a partial path that passes through a node to which a plurality of signals is input and for which an estimation in a statistical MAX is predicted to be large, that is present on a critical path having large influence on a circuit delay, and that has high possibility of improving the circuit delay, among nodes in a circuit graph is calculated by the Monte Carlo simulation instead of the block based simulation, thereby increasing speed and accuracy of delay analysis. | 05-28-2009 |

20090276745 | DUMMY METAL INSERTION PROCESSING METHOD AND APPARATUS - A method includes: before carrying out a timing verification processing of a semiconductor circuit, preliminarily superposing and arranging a dummy pattern template representing an arrangement pattern of dummy metal, onto a layout area defined by layout data while changing an origin position of the dummy pattern template to optimize the origin position of the dummy pattern template; and upon detecting that the result of the timing verification processing has no problem, superposing and arranging the dummy pattern template onto the layout area at the origin position of the dummy pattern template, to generate the layout data after inserting the dummy metal. | 11-05-2009 |

20100077367 | LAYOUT EVALUATION APPARATUS AND METHOD - An apparatus that evaluates a layout of a semiconductor integrated circuit by estimating a result of planarization in manufacturing the circuit includes a unit that divides the layout into partial areas, a unit that calculates, for each partial area, at least one of a wiring density in the partial area, a total perimeter length of wirings in the partial area, and a maximum value of differences of wiring densities in adjacent partial areas adjacent to the partial area from the wiring density in the partial area as partial area data, a unit that sets ranges of the wiring density, the total perimeter length, and the maximum value from which a height variation larger than an upper limit value is expected as critical regions based on an equation corresponding to a type of the layout, and a unit that plots the critical regions and the partial area data on a same map. | 03-25-2010 |

20100287520 | Dummy rule generating apparatus - A dummy rule generating apparatus includes a critical pattern estimating unit that determines a wiring pattern whose total perimeter length of wirings is smaller than an appropriate range based on constraints on the wirings for a circuit layout as a critical pattern. The dummy rule generating apparatus also includes a rule generating unit that generates dummy fill rules of a shape and a layout of dummy metals that increase number of dummy metals inserted in the critical pattern and decrease the number of dummy metals inserted in a wiring pattern whose total perimeter length of wirings is within an appropriate range. | 11-11-2010 |

20110239182 | AUTOMATIC CIRCUIT DESIGN TECHNIQUE - A set of pareto optimal solutions that are non-dominated solutions in a solution specification space for respective items in requirement specification is extracted with a combination of a circuit configuration including a specific function and a process constraint condition. Furthermore, pareto optimal solutions are extracted for all combinations of the circuit configuration and the process constraint condition, and pareto optimal solutions are extracted for the respective process constraint conditions. When such extracted data is distributed to designers, it is possible to reduce time to generate the pareto optimal solutions, and the designers can design the optimum circuit having a desired function by using such extracted data. | 09-29-2011 |

20120010829 | Fault diagnosis method, fault diagnosis apparatus, and computer-readable storage medium - A fault diagnosis may perform a statistical analysis based on a fault report of a semiconductor device, in order to output a feature that becomes the cause of the fault depending on a contribution of the feature to the fault. A process of grouping circuit information of the semiconductor device into N groups using one kind of feature as an index may be performed for K kinds of features, in order to group the circuit information into K×N groups. A sum total of feature quantities of partial circuits belonging to each of the groups may be output in a form of a list of learning samples. | 01-12-2012 |

20120185814 | INDICATOR CALCULATION METHOD AND APPARATUS - A method for calculating an indicator value includes: extracting features, which are mutually independent, by using data stored in a data storage unit storing, for each group of circuits implemented on a semiconductor device, the number of actual failures occurred in the group and a feature value of each feature that is a failure factor; generating an expression of a failure occurrence probability model, which represents a failure occurrence probability, which is obtained by dividing a total sum of the numbers of actual failures by the number of semiconductor devices, as a relation including a sum of products of the feature value of each of the extracted features and a corresponding coefficient, by carrying out a regression calculation using data stored in the data storage unit; and calculating an indicator value for design change of the semiconductor device from the generated expression of the failure occurrence probability model. | 07-19-2012 |

20120239347 | FAILURE DIAGNOSIS SUPPORT TECHNIQUE - The disclosed method includes: calculating a first expected value of the number of failures for each combination of a feature that is a failure factor and a first group regarding classification elements of first semiconductor devices for which a failure is analyzed and second semiconductors on which a same circuit as the first semiconductors is implemented, from first data for each first group and a predetermined expression, wherein the first data includes the number of actual failures occurred in the first group and first feature values of features; and calculating, for each feature, a first indicator value representing similarity between a distribution of the first expected values over the first groups and a distribution of the numbers of actual failures over the first groups, from the first expected value for each combination of the feature and the first group and the number of actual failures for each first group. | 09-20-2012 |