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Iyengar
Anuroop Iyengar, Bangalore IN
| Patent application number | Description | Published |
|---|---|---|
| 20090146728 | GENERIC VOLTAGE TOLERANT LOW POWER STARTUP CIRCUIT AND APPLICATIONS THEREOF - Circuits and systems including a startup circuit coupled to a reference source for providing startup current to the reference source wherein no transistor of the startup circuit experiences a stress condition and wherein the startup circuit consumes no static current following stabilized, steady-state operation of the reference source. | 06-11-2009 |
| 20100033214 | HIGH VOLTAGE INPUT RECEIVER WITH HYSTERESIS USING LOW VOLTAGE TRANSISTORS - A high voltage input receiver with hysteresis using low voltage transistors is disclosed. In one embodiment, an input receiver circuit includes a hysteresis comparator circuit, based on a plurality of low voltage transistors, for generating a first output voltage by comparing an external voltage and a reference voltage and a stress protection circuit for preventing the plurality of low voltage transistors of the hysteresis comparator circuit from exceeding their reliability limits. In addition, the reference voltage is used to set a positive trip point and a negative trip point. Moreover, the input receiver circuit includes a source follower circuit for transferring the first output voltage to an output node of the source follower circuit from a voltage level of a VDDIO to a voltage level of a VDD. | 02-11-2010 |
| 20100164591 | POWER DETECTION SYSTEM AND CIRCUIT FOR HIGH VOLTAGE SUPPLY AND LOW VOLTAGE DEVICES - A power detect system and circuit for detecting a voltage level of an input/output supply voltage (VDDIO) in a circuit of low voltage devices is disclosed. In one embodiment, the power detect system and circuit includes a voltage divider coupled between the VDDIO and a negative supply voltage (VSS) for generating a bias voltage, a first inverter coupled between a core voltage (VDD) and the VSS for generating a first node voltage based on the bias voltage, a native device coupled between the VDDIO and the VSS for generating a second node voltage based on the bias voltage, and a switch coupled between the first inverter and the native device for controlling the second node voltage based on the first node voltage. The power detect system further includes a second inverter coupled between the VDD and the VSS for generating an output voltage based on the second node voltage. | 07-01-2010 |
Rajan Iyengar, Fredericton CA
| Patent application number | Description | Published |
|---|---|---|
| 20110310773 | METHOD AND SYSTEM FOR FAIL-SAFE CALL SURVIVAL - The present invention provides a system and method for fail-safe call survival by detecting failure of an active call serving component and switching the service over to a standby component. The system and method will prevent an existing call, whether established or to be established, from being dropped due to a single point of failure within a Voice over Internet Protocol system. The continuation of the call is based on the failed component as opposed to relying on communication endpoints to re-initiate or re-route the failed call. Call recovery is initiated independent from the call path of a call. The detection of a condition or need for call recovery and the determination to initiate call recovery procedures are made without involving endpoints or intermediate points of the call. The availability and sanity of all components are continuously monitored and are tailored specifically for the duties of each component. | 12-22-2011 |
Ranganath G. Iyengar, Bangalore IN
| Patent application number | Description | Published |
|---|---|---|
| 20090327635 | Data security for use with a file system - An embodiment of the invention provides an apparatus and method for providing data security for use with a file system. The apparatus and method performs acts including: applying a mapping function to data block numbers that are associated with a file; and obtaining mapped data block numbers after applying the mapping function, wherein the mapped data block numbers are addresses of data of the file in a storage device. | 12-31-2009 |
Ranganath Gorur Iyengar, Bangalore IN
| Patent application number | Description | Published |
|---|---|---|
| 20080198771 | Method, Apparatus or Software for a Multicast Network for Providing Indications of Active Multicast Groups to one or more Multicast Receivers - A method, apparatus and software is disclosed for enabling data receivers in a multicast network to access data indicating active multicast groups that may be joined. | 08-21-2008 |
Ranganath Gorur Kirshna Iyengar, Bangalore IN
| Patent application number | Description | Published |
|---|---|---|
| 20100040058 | Systems and Methods of Configuring a Resource Pool as a Network End Point - A resource pool aggregator is disclosed. The resource pool aggregator facilitates a faster data communication between resource pools. The resource pool aggregator includes a plurality of network interfaces to receive and send data packets. A packet collector module couple of the plurality of network interfaces is included to process and route the data packets. A data store coupled to the packet collector module is provided to store IP addresses of computers in the resource pools. | 02-18-2010 |
Srinivasan Venkatachary Iyengar, Maharashtra IN
| Patent application number | Description | Published |
|---|---|---|
| 20120041989 | GENERATING ASSESSMENT DATA - Methods and systems described herein implement data generation for purposes such as data-driven assessment of an application, a process, or a system. In one implementation, seed data having one or more characteristics is received. Once received, the seed data is repeatedly transformed to generate a desired volume of an assessment data having the one or more characteristics associated with the seed data. | 02-16-2012 |
Venkatesh Iyengar, Jayanagar IN
| Patent application number | Description | Published |
|---|---|---|
| 20120101872 | METHOD AND SYSTEM FOR DETERMINING TESTING MATURITY OF AN ORGANIZATION - The invention describes a method, a system, and a computer program product for determining the maturity of a testing organization. The testing organization may be defined as an organization that specializes or involves in testing of software/software applications. The method utilizes a pre-determined model to asses the maturity level of the testing organization. In addition to providing the pre-determined model, the invention facilitates in determining the maturity level across various test dimensions of the testing organization. | 04-26-2012 |
Venkatesh Mj Iyengar, Bangalore Karnataka IN
| Patent application number | Description | Published |
|---|---|---|
| 20110320409 | GUARANTEED IN-FLIGHT SQL INSERT OPERATION SUPPORT DURING AN RAC DATABASE FAILOVER - The present invention is directed to methods and systems of implementing a guaranteed SQL insert operation. In one embodiment, the method may include initiating an SQL insert operation for a database, receiving an SQL exception indicating that a failover for the database has occurred, and in response to the SQL exception, caching the SQL insert operation and caching the SQL insert operation as an SQL merge operation. The method further includes determining that a primary key is associated with the SQL insert operation, and in response to determining that a primary key is associated with the SQL insert operation, executing the SQL merge operation. | 12-29-2011 |