| Patent application number | Description | Published |
|---|
| 20100041167 | DRUG FOR DIAGNOSING LARGE INTESTINAL CANCER AND/OR POLYP, OBSERVING POSTOPERATIVE COURSE AND MONITORING RECURRENCE - The present invention is directed to a method for diagnosing large intestinal cancer and/or polyp and a method for observing postoperative course or monitoring recurrence thereof, wherein each method includes detecting cystatin SN protein by use of an anti-cystatin SN antibody. The present invention is able to provide a kit for assaying cystatin SN, which can be used, in a simple manner, in a diagnosis performed prior to conventional barium enema examination and endoscopic examination which impose burdens on patients; as an indicator of metastasis and recurrence; and in the evaluation of therapeutic effects. The present invention provides a method for diagnosing or monitoring large intestinal cancer and/or polyp which can be performed in a simple manner, and thus can allow to design a new regimen rapidly. | 02-18-2010 |
| 20100062449 | Method Of Measuring PTX3 With High Sensitivity - To provide a method of determining vasculopathy, which is a risk factor of myocardial infarction, angiopathic dementia, etc., at an early stage thereof (i.e., mild vasculopathy). The present invention provides a method of determining the severity of mild vasculopathy, including determining PTX3 level in an assay sample by use of an anti-PTX3 monoclonal antibody. | 03-11-2010 |
| 20120003149 | NOVEL MONOCLONAL ANTIBODY, AND USE THEREOF - [Theme] To provide a monoclonal antibody against human GPR87. Also, to provide a novel means for diagnosing or treating a malignant tumor. | 01-05-2012 |
| Patent application number | Description | Published |
|---|
| 20080313391 | SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR DEVICE - A semiconductor memory device, including: a cell array block including a plurality of memory cells arranged therein; and a controller, wherein the controller controls the semiconductor memory device so that: an operation of reading out data from a second region in the cell array block is initiated before completion of an operation of outputting data read out from a first region in the cell array block; and the data read out from the second region is output successively after the completion of the operation of outputting data read out from the first region. | 12-18-2008 |
| 20090016093 | MEMORY SYSTEM AND SEMICONDUCTOR INTEGRATED CIRCUIT - A ferroelectric memory provided in a memory system stores in advance set data for data write time to memory cells. The set data include two types of data that differ between in a power-on state and in a power-off instruction time. When power is turned on, the set data that are stored in the ferroelectric memory are stored and retained in a latch circuit by a control circuit. Based on the set data retained in the latch circuit, data writing is performed in the ferroelectric memory respectively in the power-on state and in the power-off instruction time. Thus, operations of the ferroelectric memory can be controlled with desired operation timings according to operating conditions for each memory system. Excessive stress application to the ferroelectric memory during the power-on state is prevented and endurance deterioration is suppressed, while data retention characteristics after power-off are improved. | 01-15-2009 |
| 20090175065 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor memory device including a ferroelectric memory includes: a nonvolatile memory having higher data retention capability under high temperature than the ferroelectric memory; and a connection circuit for switching between connection and disconnection of the ferroelectric memory and the nonvolatile memory. The ferroelectric memory receives, through the connection circuit, at least part of data which is unique to the device and which has been written into the nonvolatile memory, and retains the received data. | 07-09-2009 |
| 20090210612 | MEMORY CONTROLLER, NONVOLATILE MEMORY DEVICE, AND NONVOLATILE MEMORY SYSTEM - In rewriting processing of logical sectors, data of the transferred logical sectors are temporarily stored in a memory buffer. When the buffer memory has been full filled with data, the data is written into a flash memory. In rewriting processing for the flash memory including a writing unit (page) having a capacity larger than a minimum writing unit (sector) from outside, the number of executions of the evacuation processing can be reduced and the fast data rewriting can be performed. Thus, it is possible to rationalize the evacuation processing for old data caused in the rewriting in units of sectors and to improve the data rewriting speed. | 08-20-2009 |
| 20090244951 | SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY SYSTEM - A semiconductor memory device includes a plurality of memory cell arrays each including a plurality of memory cells arranged in a matrix pattern, and a plurality of cell plate lines each being shared by the memory cell arrays, each of the cell plate lines corresponding to each of rows of the memory cells and each of the cell plate lines being connected to the memory cells of a corresponding one of the rows. Each of the memory cell arrays includes a plurality of word lines each of which corresponds to each of the rows of the memory cells in the memory cell array. The number of the memory cells connected to each of the cell plate lines is larger than the number of the memory cells connected to one of the word lines corresponding to the each of the cell plate lines. | 10-01-2009 |
| 20100023840 | ECC CIRCUIT, SEMICONDUCTOR MEMORY DEVICE, MEMORY SYSTEM - A syndrome generation section generates a syndrome from input data having d bits of data bits and k bits of parity bits. A syndrome table stores a syndrome pattern indicating that no error has occurred in the input data and syndrome patterns indicating an error position. A comparison section compares the syndrome generated by the syndrome generation section with the syndrome patterns in the syndrome table, outputs a match signal when a syndrome pattern matching the syndrome exists, and outputs a no-match signal when no syndrome pattern matching the syndrome exists. An error correction section corrects the error in the input data based on the match signal from the comparison section. | 01-28-2010 |
| 20110255328 | SEMICONDUCTOR MEMORY DEVICE - The demand for reducing the size and increasing the degree of integration of semiconductor memory devices has increased. In a semiconductor memory device, a smoothing capacitor which has to be provided therein for stabilizing a power supply voltage etc. is formed in an underlying layer of memory cells A and B to overlap the two memory cells A and B which are adjacent each other. Thus, an area occupied by the smoothing capacitor having a large capacity can be reduced to increase the degree of integration, and the smoothing capacitor having a large capacity can be provided in the semiconductor memory device. | 10-20-2011 |
| 20120075905 | SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor memory device includes a plurality of memory cells connected to a common bit line, a plurality of select lines each configured to select at least one of the memory cells, a plurality of drive circuits each configured to drive at least one of the select lines, a sense amplifier configured to amplify a voltage occurring at the bit line depending on data stored in the selected memory cell. A memory region where the memory cells are provided has a first region and a second region. When the first region is read, a larger number of the select lines are simultaneously driven by the corresponding common drive circuit than those in the second region, and a larger number of the memory cells are simultaneously selected than those in the second region. | 03-29-2012 |
