Patent application number | Description | Published |
20090263792 | ATOPIC DERMATITIS MARKER AND TECHNIQUE OF USING THE SAME - It is an object of the present invention to find substances that can be used as disease markers for atopic dermatitis and the present invention provides a method for determining atopic dermatitis, including measurement of the expression of specific proteins and/or their genes in skin cells and/or skin tissues, wherein the specific proteins change their expression with inflammation caused by atopic dermatitis or change their expression according to the degree of predisposition to atopic dermatitis. The present invention also provides a kit for determining the degree of inflammation of atopic dermatitis or risk of developing atopic dermatitis, as well as a method for determining substances effective in the treatment and/or prevention of atopic dermatitis. | 10-22-2009 |
20130120734 | LASER RADAR APPARATUS - A laser radar apparatus includes a light source; a light scanning unit configured to scan light irradiated from the light source; a light receiving unit configured to receive light that is reflected by an object, the light being irradiated from the light scanning unit onto the object and reflected by the object; and a porous member arranged between the object and the light receiving unit, the porous member including plural through holes. | 05-16-2013 |
20130135859 | LIGHT IRRADIATOR, IMAGE SCANNER, AND IMAGE FORMING APPARATUS - A light irradiator including multiple point light sources arranged in a straight line, a light-transmissive light guiding member provided in front of the point light sources in an emission direction of beams of light emitted from the point light sources, the light guiding member guiding the beams of light in a predetermined direction toward a surface to be irradiated; and two or more protrusions protruding toward the point light sources, provided on a light entering surface of the light guiding member and arranged in the same direction as the point light sources. The light guiding member and the point light sources are positioned such that a distance between the protrusions provided to the light guiding member and irradiation surfaces of the point light sources is equal at two positions. | 05-30-2013 |
20140233077 | LIGHT IRRADIATION SYSTEM, IMAGE SCANNING APPARATUS, AND IMAGE FORMING APPARATUS - An light irradiation system for irradiating light a document face includes a light source; a light guiding member to guide light emitted from the light source; and a reflector to reflect a part of light exiting from the light guiding member to the document face. A direction that emission light intensity of the light emitted from the light source becomes the strongest is different from a direction extending from the light source to an irradiation area. The irradiation area is irradiated by a reflection light reflected by the reflector, and a direct light exiting from the light guiding member without reflection at the reflector. The light guiding member including an incidence surface, an exit surface, and a light guiding part including a total reflection face. Light quantity irradiated to the document face by reflection light is smaller than light quantity irradiated to the document face by direct light. | 08-21-2014 |
20140268254 | LIGHT IRRADIATION SYSTEM, IMAGE SCANNING APPARATUS, AND IMAGE FORMING APPARATUS - A light irradiation system for irradiating light to an irradiation area extending in a main scanning direction of a document face when placed on an image scanning apparatus includes a light source; a light guiding member to guide light emitted from the light source; and a reflector to reflect a part of light exiting from the light guiding member to the document face. The irradiation area is irradiated by the reflection light reflected by the reflector and a direct light exiting from the light guiding member without reflection at the reflector. The light guiding member includes an incidence surface where the light from the light source enters; and an exit surface where the light entered from the incidence surface exits. The reflector is disposed at a position in a direction that light intensity of light emitting from the light source becomes the strongest. | 09-18-2014 |
20150062668 | LIGHT IRRADIATION DEVICE AND IMAGE FORMING APPARATUS - A light irradiation device includes: a light source to output diffused light; and a light guide member to guide the diffused light to an irradiation point. The light guide member includes an incidence surface which the diffused light enters, a first emission surface to emit the entered diffused light, while further diffusing the entered diffused light with a first diffusion characteristic to emit the diffused light at a first diffusion angle, and a second emission surface to emit the entered diffused light, while further diffusing the entered diffused light with a second diffusion characteristics to emit the diffused light at a second diffusion angle. The second diffusion angle provided by the second diffusion characteristic is smaller than the first diffusion angle provided by the first diffusion characteristic. | 03-05-2015 |
Patent application number | Description | Published |
20120269472 | ROLLING BEARING - There is provided a rolling bearing which inhibits spalling of a rolling element and has a long service life even under rigorous environments. The rolling bearing comprises grease for lubricating rolling contact parts and/or sliding contact parts between a first raceway surface and a rolling elements and/or between a second raceway surface and a rolling elements, wherein the grease comprises a base oil, a thickener and an extreme pressure additive, the thickener is a diurea compound obtained by allowing an amine mixture comprising alkylphenylamine, alkyl group of which has 8 to 16 carbon atoms, and cyclohexylamine, to react with a diisocyanate compound, an amount of cyclohexylamine in the total amount of the alkylphenylamine and cyclohexylamine is from 91 to 99% by mole, and a reaction temperature of the extreme pressure additive with iron is 260° C. or lower. | 10-25-2012 |
20120270762 | GREASE COMPOSITION - There is provided a grease composition, in which a grease film on the surface of the applied part is made thicker compared with conventional grease compositions, this thickness is maintained for a long period of time, and as a result, a longer service life against seizure compared with conventional grease compositions is assured. The grease composition comprises a base oil and a thickener, wherein the thickener is a diurea compound obtained by allowing an amine mixture comprising alkylphenylamine, an alkyl group of which has 8 to 16 carbon atoms, and cyclohexylamine, to react with a diisocyanate compound, and an amount of cyclohexylamine in the total amount of the alkylphenylamine and cyclohexylamine is from 91 to 99% by mole. | 10-25-2012 |
20130137612 | GREASE COMPOSITION AND BEARING - The present invention provides a grease composition which has excellent conductivity and can rapidly remove static electricity generated by using a bearing. The grease composition comprises a base oil, a thickener and a tungsten disulfide powder, wherein the average particle diameter of the tungsten disulfide powder is 0.5 to 5.0 μm and the amount of tungsten disulfide powder based on 100 parts by mass of the total amount of base oil and thickener is 2.0 to 4.0 parts by mass. | 05-30-2013 |
20150023622 | GREASE COMPOSITION AND ROLLING DEVICE - A grease composition which is excellent in seizure resistance can be provided without deteriorating resistance to stirring, in the rolling device, and a rolling device in which the grease composition intervenes to a predetermined portion can be also provided by use of a grease composition comprising a base oil, a thickener and an amine antioxidant, the thickener being a diurea compound obtained by allowing an amine mixture comprising alkylphenylamine, an alkyl group of which has 8 to 16 carbon atoms, and cyclohexylamine, to react with a diisocyanate compound, the amount of cyclohexylamine in the amine mixture being 91 to 99% by mole, and the amount of the amine antioxidant in the grease composition being 21% by mass or more. | 01-22-2015 |
20150078687 | GREASE COMPOSITION AND ROLLING DEVICE - A grease composition which is excellent in seizure resistance can be provided without deteriorating resistance to stirring in the rolling device, and a rolling device in which the grease composition intervenes to a predetermined portion can be also provided by use of a grease composition comprising a base oil and a thickener, the thickener being a diurea compound obtained by allowing an amine mixture comprising alkylphenylamine, an alkyl group of which has 8 to 16 carbon atoms, and cyclohexylamine, to react with a diisocyanate compound, the amount of cyclohexylamine in the amine mixture being 80% by mole or more and less than 91% by mole, and a worked penetration being 300 to 330. | 03-19-2015 |
Patent application number | Description | Published |
20130194041 | AUTOMATIC GAIN CONTROL DEVICE AND METHOD, POWER ADJUSTING DEVICE AND RADIO TRANSMITTING SYSTEM - An automatic gain control device includes: a variable gain adjusting unit, for adjusting an input signal by a variable gain and outputting an adjustment result; an analog-digital converting unit, for performing analog-digital conversion on the adjustment result to obtain an analog-digital conversion result; and a gain determining unit, for determining a distribution status over a predetermined period of time of a maximum or a minimum of the analog-digital conversion result, comparing the distribution status with a first distribution condition, and if the distribution status meets the first distribution condition, then keeping the variable gain unchanged, otherwise changing the variable gain and determining newly a distribution status until the newly determined distribution status meets a second distribution condition which is at least as strict as the first distribution condition. | 08-01-2013 |
20140050281 | METHOD AND APPARATUS FOR CONTROLLING UPDATE OF DIGITAL PRE-DISTORTION COEFFICIENT - Embodiments of the present invention provide a method and apparatus for controlling update of digital pre-distortion (DPD) coefficient. The apparatus is applicable to a digital power control system, wherein the apparatus comprises: an update controlling unit configured to determine a group of fully-trained DPD coefficients among a plurality of DPD coefficients; and a DPD coefficient generating unit configured to update adaptively the group of fully-trained DPD coefficients according to the result of judgment of the update controlling unit. With the embodiment of the present invention, the DPD coefficients are allowed to be updated after being judged as being able to be fully trained according to power distribution information of DPD input signals, or according to address distribution information of an LUT, or according to average power of output of an HPA; otherwise, they are not allowed to be updated, thereby efficiently preventing DPD abnormality resulted from unfull training of coefficients in being updated. | 02-20-2014 |
20140094133 | TEMPERATURE COMPENSATION METHOD AND APPARATUS FOR RECEIVED SIGNAL STRENGTH INDICATOR - Embodiments of the present invention provide a temperature compensation method and apparatus for a received signal strength indicator. The apparatus comprises a temperature sensor configured to measure a current temperature; and a digital compensation module configured to select a temperature compensation coefficient from prestored temperature compensation coefficients corresponding to a normal temperature, a low temperature and a high temperature according to the current temperature, and perform temperature compensation on output signals of the RSSI according to the selected temperature compensation coefficient. With the method and apparatus of the embodiments of the present invention, the accurate power values of the input signals of the RSSI under any temperatures can be obtained by measuring the characteristics of the RSSI under the predefined three temperatures, and using an interpolation method to compensate for the temperature characteristics of the RSSI. In comparison with the relevant art, the size of the storage is decreased and the accuracy of temperature compensation is improved. | 04-03-2014 |
20150061773 | DIGITAL PREDISTORTION APPARATUS AND METHOD - A digital predistortion apparatus comprising: a nonlinear device; a memory effect compensator; a constant value characteristic acquirer; a cost function generator; and a coefficient updater is described. | 03-05-2015 |
20150071382 | DIGITAL PRE-DISTORTION TRANSMITTER AND METHOD FOR CONTROLLING THE SAME - The embodiments of the present disclosure provide a digital pre-distortion transmitter and a method for controlling the same, which increase the efficiency of the power amplifier and improve the linearity of the transmitter. The digital pre-distortion transmitter includes: a pre-distortion unit configured to update a pre-distortion coefficient required by pre-distortion processing, and perform the pre-distortion processing on a baseband signal; a signal process and transmit unit configured to perform signal processing on the pre-distortion-processed baseband signal and transmission thereof; and a feedback signal process unit configured to process a feedback signal of the signal transmitted by the signal process and transmit unit, so as to supply a dynamic drain voltage to a power amplifier in the signal process and transmit unit by using the processed feedback signal; wherein, the pre-distortion unit updates the pre-distortion coefficient by using the feedback signal processed by the feedback signal process unit. | 03-12-2015 |
20150280944 | OPTIMIZING APPARATUS AND METHOD FOR A PULSE SHAPING FILTER AND A TRANSMITTER - Embodiments of the present invention provide an optimizing apparatus and method for a pulse shaping filter and a transmitter. The apparatus includes: a first determining unit configured to determine an initial peak-to-average power ratio threshold of the pulse shaping filter, and determine an initial filter coefficient of the pulse shaping filter according to the initial peak-to-average power ratio threshold; a second determining unit configured to determine a constraint condition for optimizing the pulse shaping filter according to the initial peak-to-average power ratio threshold and the initial filter coefficient of the pulse shaping filter; wherein the constraint condition comprises a threshold constraint in a filter coefficient sign domain; and an optimizing unit configured to adjust the initial peak-to-average power ratio threshold and the initial filter coefficient of the pulse shaping filter in a case where the constraint condition is satisfied, until a predefined condition is satisfied, so as to obtain an optimized filter coefficient of the pulse shaping filter. Optimization according to the constraint condition including the threshold constraint in the filter coefficient sign domain can simply and conveniently obtain a pulse shaping filter of a low peak-to-average power ratio, thereby efficiently lowering a peak-to-average power ratio for transmitting signals without changing the structure of an existing communication system. | 10-01-2015 |
Patent application number | Description | Published |
20130119469 | SEMICONDUCTOR DEVICE - Improvements are achieved in the characteristics of a semiconductor device including SRAM memory cells. Under an active region in which an access transistor forming an SRAM is disposed, a p-type semiconductor region is disposed via an insulating layer such that the bottom portion and side portions thereof come in contact with an n-type semiconductor region. Thus, the p-type semiconductor region is pn-isolated from the n-type semiconductor region, and the gate electrode of the access transistor is coupled to the p-type semiconductor region. The coupling is achieved by a shared plug which is an indiscrete conductive film extending from over the gate electrode of the access transistor to over the p-type semiconductor region. As a result, when the access transistor is in an ON state, a potential in the p-type semiconductor region serving as a back gate simultaneously increases to allow an increase in an ON current for the transistor. | 05-16-2013 |
20130161753 | SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD THEREOF - The performances of a semiconductor device are improved. The device includes a first MISFET in which hafnium is added to the gate electrode side of a first gate insulation film including silicon oxynitride, and a second MISFET in which hafnium is added to the gate electrode side of a second gate insulation film including silicon oxynitride. The hafnium concentration in the second gate insulation film of the second MISFET is set smaller than the hafnium concentration in the first gate insulation film of the first MISFET; and the nitrogen concentration in the second gate insulation film of the second MISFET is set smaller than the nitrogen concentration in the first gate insulation film of the first MISFET. As a result, the threshold voltage of the second MISFET is adjusted to be smaller than the threshold voltage of the first MISFET. | 06-27-2013 |
20130175611 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An area in a top view of a region where a low-voltage field effect transistor is formed is reduced, and an area in a top view of a region where a high-voltage field effect transistor is formed is reduced. An active region where the low-voltage field effect transistors (first nMIS and first pMIS) are formed is constituted by a first convex portion of a semiconductor substrate that projects from a surface of an element isolation portion, and an active region where the high-voltage field effect transistors (second nMIS and second pMIS) are formed is constituted by a second convex portion of the semiconductor substrate that projects from the surface of the element isolation portion, and a trench portion formed in the semiconductor substrate. | 07-11-2013 |
20140319618 | SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD THEREOF - The performances of a semiconductor device are improved. The device includes a first MISFET in which hafnium is added to the gate electrode side of a first gate insulation film including silicon oxynitride, and a second MISFET in which hafnium is added to the gate electrode side of a second gate insulation film including silicon oxynitride. The hafnium concentration in the second gate insulation film of the second MISFET is set smaller than the hafnium concentration in the first gate insulation film of the first MISFET; and the nitrogen concentration in the second gate insulation film of the second MISFET is set smaller than the nitrogen concentration in the first gate insulation film of the first MISFET. As a result, the threshold voltage of the second MISFET is adjusted to be smaller than the threshold voltage of the first MISFET. | 10-30-2014 |
20150111348 | Semiconductor Device and Manufacturing Method of the Same - Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. | 04-23-2015 |
20150137239 | Semiconductor Device and Method of Manufacturing the Same - To suppress performance degradation of a semiconductor device, when the width of a first active region having a first field effect transistor formed therein is smaller than the width of a second active region having a second field effect transistor formed therein, the height of a surface of a first raised source layer of the first field effect transistor is made larger than the height of a surface of a second raised source layer of the second field effect transistor. Moreover, the height of a first surface of a raised drain layer of the first field effect transistor is made larger than a surface of a second raised drain layer of the second field effect transistor. | 05-21-2015 |
20150221668 | SOI SRAM HAVING WELL REGIONS WITH OPPOSITE CONDUCTIVITY - A semiconductor device with an SRAM memory cell having improved characteristics. | 08-06-2015 |
20150287746 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - In a step F | 10-08-2015 |
Patent application number | Description | Published |
20110031552 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - To provide, in FINFET whose threshold voltage is determined essentially by the work function of a gate electrode, a technology capable of adjusting the threshold voltage of FINFET without changing the material of the gate electrode. FINFET is formed over an SOI substrate comprised of a substrate layer, a buried insulating layer formed over the substrate layer, and a silicon layer formed over the buried insulating layer. The substrate layer has therein a first semiconductor region contiguous to the buried insulating layer. The silicon layer of the SOI substrate is processed into a fin. A ratio of the height of the fin to the width of the fin is adjusted to fall within a range of from 1 or greater but not greater than 2. In addition, a voltage can be applied to the first semiconductor region. | 02-10-2011 |
20110049629 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - To provide a technique capable of achieving improvement of the parasitic resistance in FINFETs. In the FINFET in the present invention, a sidewall is formed of a laminated film. Specifically, the sidewall is composed of a first silicon oxide film, a silicon nitride film formed over the first silicon oxide film, and a second silicon oxide film formed over the silicon nitride film. The sidewall is not formed on the side wall of a fin. Thus, in the present invention, the sidewall is formed on the side wall of a gate electrode and the sidewall is not formed on the side wall of the fin. | 03-03-2011 |
20110186936 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - a method for producing a semiconductor device provided in such a manner that a first layer and a second layer are laminated to ensure that their TSVs are arranged in almost a straight line, including: first layer production steps including steps of preparing a substrate, forming a transistor of an input/output circuit on an upper surface of the substrate, forming an insulation layer so as to cover the transistor, and forming a TSV in the insulation layer; second layer production steps including steps of preparing a substrate, forming a transistor of a logic circuit on an upper surface of the substrate, forming an insulation layer so as to cover the transistor, and forming a TSV in the insulation layer; a connection step of connecting surfaces of the first layer and the second layer on a side opposite to substrates of the first layer and the second layer to ensure that the TSV of the first layer and the TSV of the second layer are arranged in almost a straight line; and a step of removing the substrate of the first layer. | 08-04-2011 |
20110215423 | SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD THEREOF - There are provided a semiconductor device which can be miniaturized without being deteriorated in characteristics, and a manufacturing method thereof. The semiconductor device includes a semiconductor substrate having a main surface, a source region and a drain region formed apart from each other in the main surface, a gate electrode layer formed over the main surface sandwiched between the source region and the drain region, a first conductive layer formed so as to be in contact with the surface of the source region, and a second conductive layer formed so as to be in contact with the surface of the drain region. A recess is formed in the main surface so as to extend from the contact region between the first conductive layer and the source region through a part underlying the gate electrode layer to the contact region between the second conductive layer and the drain region. | 09-08-2011 |
20120007151 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A high breakdown voltage circuit containing a high breakdown voltage MOSFET in LSI, unlike a quintessential internal circuit, has an operating voltage fixed in a high state due to the relation with the outside and, therefore, miniaturization by the voltage lowering can not be applied, differing from ordinary cases. Consequently, the voltage lowering of an internal circuit part results in a furthermore enlargement of occupying area in the chip. The present inventors evaluated various measures for the problem, and made it clear that such problems as compatibility with the CMOSFET circuit configuration and device configuration, etc. constitute obstacles. | 01-12-2012 |
20120061761 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES - Logic transistors (MOSFETs, MISFETs) in core portions of integrated circuits can be microminiaturized by scaling operating voltage as their generation advances. However, since transistors (MOSFETs, MISFETs) in high-breakdown voltage portions operate on relatively high power supply voltage, it is difficult to reduce their size. Similarly, electrostatic discharge (ESD) protection circuits in power supply cells protect the elements in a semiconductor integrated circuit against static electricity (foreign surge); therefore, they are indispensably required to be high in breakdown voltage and call for a large area for dissipating electric charges. To microminiaturize integrated circuits, therefore, a transistor structure that enables microminiaturization is indispensable. To solve the above problem, a semiconductor integrated circuit device having in its ESD protection circuit portion a CMIS inverter made up of a pair of MISFETs having a source/drain asymmetric structure and including a halo region only on the source side is provided. | 03-15-2012 |
20120146148 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A bulk & SOI hybrid CMIS device, in which an I/O bulk part and a core logic SOI part are mounted, needs a number of gate stacks to optimize threshold voltage control and causes a problem that the process and structure become complicated. | 06-14-2012 |
20130020644 | SEMICONDUCTOR DEVICE - A semiconductor device with an SRAM memory cell having improved characteristics. Below an active region in which a driver transistor including a SRAM is placed, an n type back gate region surrounded by an element isolation region is provided via an insulating layer. It is coupled to the gate electrode of the driver transistor. A p well region is provided below the n type back gate region and at least partially extends to a position deeper than the element isolation region. It is fixed at a grounding potential. Such a configuration makes it possible to control the threshold potential of the transistor to be high when the transistor is ON and to be low when the transistor is OFF; and control so as not to apply a forward bias to the PN junction between the p well region and the n type back gate region. | 01-24-2013 |
20130119470 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Characteristics of a semiconductor device are improved. A semiconductor device of the present invention includes: (a) a MISFET arranged in an active region formed of a semiconductor region surrounded by an element isolation region; and (b) an insulating layer arranged below the active region. Further, the semiconductor device includes: (c) a p-type semiconductor region arranged below the active region so as to interpose the insulating layer; and (d) an n-type semiconductor region whose conductivity type is opposite to the p-type, arranged below the p-type semiconductor region. And, the p-type semiconductor region includes a connection region extending from below the insulating layer, and the p-type semiconductor region and a gate electrode of the MISFET are connected to each other by a shared plug which is an integrally-formed conductive film extending from above the gate electrode to above the connection region. | 05-16-2013 |
20130140669 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A first MISFET which is a semiconductor element is formed on an SOI substrate. The SOI substrate includes a supporting substrate which is a base, BOX layer which is an insulating layer formed on a main surface (surface) of the supporting substrate, that is, a buried oxide film; and an SOI layer which is a semiconductor layer formed on the BOX layer. The first MISFET as a semiconductor element is formed to the SOI layer. In an isolation region, an isolation groove is formed penetrating though the SOI layer and the BOX layer so that a bottom surface of the groove is positioned in the middle of a thickness of the supporting substrate. An isolation film is buried in the isolation groove being formed. Then, an oxidation resistant film is interposed between the BOX layer and the isolation film. | 06-06-2013 |
20130187230 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. | 07-25-2013 |
20130230964 | MANUFACTURING METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A method for manufacturing a semiconductor integrated circuit device includes the step of forming an SOI device region and a bulk device region on an SOI type semiconductor wafer. The method includes: removing a BOX layer and an SOI layer in a bulk device region; and thereafter forming an STI region in both the SOI device region and the bulk device region. In the method, the STI region in the SOI device region is formed to extend through the BOX layer. | 09-05-2013 |
20130264644 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer. | 10-10-2013 |
20140042529 | SEMICONDUCTOR DEVICE AND MANUFACTRUING METHOD OF THE SAME - A semiconductor device is manufactured by using an SOI substrate having an insulating layer on a substrate and a semiconductor layer on the insulating layer. The semiconductor device is provided with a gate electrode formed on the semiconductor layer via a gate insulating film, a sidewall spacer formed on a sidewall of the gate electrode, a semiconductor layer for source/drain that is epitaxially grown on the semiconductor layer, and a sidewall spacer formed on a sidewall of the semiconductor layer. | 02-13-2014 |
20140042552 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - Provided is a semiconductor device having an insulating gate field effect transistor equipped with a metal oxide film in a portion, on the side of a source region, between a gate insulating film and a gate electrode. The metal oxide film is provided above a p | 02-13-2014 |
20140203364 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device having an n channel MISFET formed on an SOI substrate including a support substrate, an insulating layer formed on the support substrate and a silicon layer formed on the insulating layer has the following structure. An impurity region for threshold adjustment is provided in the support substrate of a gate electrode so that the silicon layer contains carbon. The threshold value can be adjusted by the semiconductor region for threshold adjustment in this manner. Further, by providing the silicon layer containing carbon, even when the impurity of the semiconductor region for threshold adjustment is diffused to the silicon layer across the insulating layer, the impurity is inactivated by the carbon implanted into the silicon layer. As a result, the fluctuation of the transistor characteristics, for example, the fluctuation of the threshold voltage of the MISFET can be reduced. | 07-24-2014 |
20140375379 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device has, as a current monitor circuit, a circuit in which n-channel type MISFETs are connected in series with each other. Based on a delay time of a speed monitor circuit in a state where a substrate bias is being applied to the p-channel type MISFETs, a first voltage value of a first substrate bias to be applied to the p-channel type MISFETs is determined. Next, based on a current flowing through an n-channel type MISFET in a state where the first substrate bias is being applied to the p-channel type MISFETs of the current monitor circuit and a second substrate bias is being applied to the n-channel type MISFETs of the current monitor circuit, a second voltage value of the second substrate bias to be applied to the n-channel type MISFETs is determined. | 12-25-2014 |
20150061006 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In an SOI substrate having a semiconductor layer formed on the semiconductor substrate via an insulating layer, a MISFET is formed in each of the semiconductor layer in an nMIS formation region and a pMIS formation region. In power feeding regions, the semiconductor layer and the insulating layer are removed. In the semiconductor substrate, a p-type semiconductor region is formed so as to include the nMIS formation region and one of the power feeding regions, and an n-type semiconductor region is formed so as to include a pMIS formation region and the other one of the power feeding regions. In the semiconductor substrate, a p-type well having lower impurity concentration than the p-type semiconductor region is formed so as to contain the p-type semiconductor region, and an n-type well having lower impurity concentration than the n-type semiconductor region is formed so as to contain the n-type semiconductor region. | 03-05-2015 |
20150084064 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The semiconductor device has a gate electrode GE formed on a substrate via a gate insulating film GI and a source/drain semiconductor layer EP | 03-26-2015 |
20150221560 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Characteristics of a semiconductor device are improved. A semiconductor device of the present invention includes: (a) a MISFET arranged in an active region formed of a semiconductor region surrounded by an element isolation region; and (b) an insulating layer arranged below the active region. Further, the semiconductor device includes: (c) a p-type semiconductor region arranged below the active region so as to interpose the insulating layer; and (d) an n-type semiconductor region whose conductivity type is opposite to the p-type, arranged below the p-type semiconductor region. And, the p-type semiconductor region includes a connection region extending from below the insulating layer, and the p-type semiconductor region and a gate electrode of the MISFET are connected to each other by a shared plug which is an integrally-formed conductive film extending from above the gate electrode to above the connection region. | 08-06-2015 |
20150325673 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device is manufactured by using an SOI substrate having an insulating layer on a substrate and a semiconductor layer on the insulating layer. The semiconductor device is provided with a gate electrode formed on the semiconductor layer via a gate insulating film, a sidewall spacer formed on a sidewall of the gate electrode, a semiconductor layer for source/drain that is epitaxially grown on the semiconductor layer, and a sidewall spacer formed on a sidewall of the semiconductor layer. | 11-12-2015 |