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Iwaki, Kanagawa
Haruhi Iwaki, Kanagawa JP
| Patent application number | Description | Published |
|---|---|---|
| 20100247443 | EFFECTIVENESS EVALUATING METHOD, EFFECTIVENESS EVALUATING DEVICE, AND EFFECTIVENESS EVALUATING PROGRAM FOR EXTERNAL PREPARATION FOR SKIN - An effectiveness evaluating method evaluates effectiveness of an external preparation for skin for protection against ultraviolet irradiation after the external preparation is applied to the skin. The method includes a measurement step of measuring an amount of urocanic acid in a horny cell layer by Raman spectroscopy both before and after the application of the external preparation and both before and after exposure to ultraviolet irradiation, an index derivation step of computing at least one index for evaluating the effectiveness of the external preparation based on results of the measurement obtained in the measurement step, and an evaluation step of evaluating the effectiveness of the external preparation by using the index obtained in the index derivation step. | 09-30-2010 |
| 20110091387 | METHODS AND COMPOSITIONS FOR REDUCING SKIN DAMAGE - The RhoE GTPase pathway has been identified as a target for screening and treatment methods for the prevention and/or reduction of short- and long-term UVB-induced skin damage, e.g., the prevention and/or reduction of UVB-induced wrinkles. The invention thus features screening and treatment methods for prevention or reduction of UVB-induced sin damage, and related compositions, e.g., cosmetic compositions. | 04-21-2011 |
Hirokazu Iwaki, Kanagawa JP
| Patent application number | Description | Published |
|---|---|---|
| 20110245423 | FLUORORUBBER COMPOSITION AND PROCESS FOR PRODUCING CROSSLINKED FLUORORUBBER - [Problem] To provide a fluororubber composition which (1) achieves an excellent shock absorbing property upon collision with an arm, (2) achieves non-tackiness, (3) is clean, and (4) is free of halogen substance (chlorine); and a method for producing a crosslinked fluororubber product. | 10-06-2011 |
Hiroyuki Iwaki, Kanagawa JP
| Patent application number | Description | Published |
|---|---|---|
| 20080303931 | Data transfer circuit, solid-state imaging device and camera system - Disclosed herein is a data transfer circuit including, a plurality of data transfer lines, a plurality of data outputting sections, a plurality of data holding sections, a data-acquiring-clock supplying section a clock supplying section, and a column scan section. | 12-11-2008 |
| 20110115959 | Solid-state imaging device, method of driving the device, and camera system - A solid-state imaging device includes: a pixel section formed by pixels performing photoelectric conversion arranged in a matrix; a pixel signal readout section capable of column-parallel processing including an A/D conversion function for reading out a pixel signal from the pixel section and performing analog-digital conversion of the signal, the pixels being read in groups; a voltage sampling section sampling a bias voltage generated by an internal or external voltage generating circuit for a period in accordance with a control signal and supplying the sampled bias voltage to the pixel signal readout section; and a control section controlling the signal readout operation of the pixel signal readout section and the voltage sampling operation of the voltage sampling section. The pixel signal readout section includes a functional portion. The control section exercises control such that the voltage sampling operation is performed in a period other than at least either of a period in which an analog signal is read out or in which A/D conversion is carried out. | 05-19-2011 |
Takashi Iwaki, Kanagawa JP
| Patent application number | Description | Published |
|---|---|---|
| 20110103095 | LIGHT GUIDE PLATE AND METHOD FOR MANUFACTURING LIGHT GUIDE PLATE - A light guide plate that uses a resin film as a material for the light guide plate, that has a reflecting or scattering pattern formed by printing, and that guides a light propagating in the film to exit and emerge from the front surface thereof. The light guide plate is thinner and highly flexible, and has high reliability and durability. A base material of the light guide plate is formed from a thermosetting polyurethane sheet with a thickness of 0.4 mm or less. When a dot pattern is formed by ink-jetting, a white UV curable ink, for which the thermosetting polyurethane exhibits a swellability such that the thermosetting polyurethane increases by 10% or more in weight as a result of being soaked in the ink for one hour at a room temperature, is used as the ink. | 05-05-2011 |
Takayuki Iwaki, Kanagawa JP
| Patent application number | Description | Published |
|---|---|---|
| 20090057893 | Semiconductor apparatus - In order to solve a problem of occurrence of delamination of interlayer film due to occurrence of a crack in an LSI wiring layer in a UBM lower layer immediately under a solder bump in an outer periphery of an LSI chip, a semiconductor apparatus of the present invention includes a stress boundary between compressive stress and tensile stress in an LSI wiring layer of a bump lower layer and in order to alleviate the stress present in the bump lower layer tensile stress material is arranged on a compressive stress side or compressive stress material is arranged on a tensile stress side with a stress boundary of the LSI wiring layer as a boundary. | 03-05-2009 |
| 20090134493 | Semiconductor device and method of manufacturing the same - Provided is a semiconductor device including a MIM capacitor, and having excellent waterproof property and antioxidant property even when being formed between wiring layers. The semiconductor device includes a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a first wiring layer embedded in the first insulating film, a wiring cap film for covering the first wiring layer, the MIM capacitor formed on the wiring cap film, a hydrogen barrier film for covering the MIM capacitor, a second insulating film formed on the hydrogen barrier film, conductive plugs passing through the second insulating film and the hydrogen barrier film, one of which being connected to an upper electrode of the MIM capacitor and the other of which being connected to a lower electrode of the MIM capacitor, and a second wiring layer connected to the conductive plugs, and the upper and lower electrodes of the MIM capacitor. | 05-28-2009 |
| 20100270643 | Semiconductor device and layout method therefor - Provided is a semiconductor device including: an MIM capacitor that includes a lower electrode, an upper electrode, and a capacitor insulating film formed between the lower electrode and the upper electrode; a first via hole that connects to the lower electrode and extends in a normal upward direction of a principal surface of the lower electrode; a second via hole that connects to the upper electrode and extends in a normal upward direction of a principal surface of the upper electrode; and a plurality of lower wiring lines that are formed under the lower electrode, in which formation areas of the first and second via holes overlap formation areas of the plurality of lower wiring lines when viewed in the normal direction of the principal surface of the upper electrode. | 10-28-2010 |
| 20100301451 | Semiconductor device, lower layer wiring designing device, method of designing lower layer wiring and computer program - A semiconductor device includes a lower layer wiring layer, an MIM capacitors and an upper layer wiring layer. The lower layer wiring layer includes a plurality of lower layer wirings. The MIM capacitor is formed above the lower layer wiring layer. The MIM capacitor includes a lower electrode, a capacity dielectric film and an upper electrode which are layered from underneath in this order. A planar form of the upper electrode is smaller than that of the lower electrode. The upper layer wiring layer includes a plurality of upper layer wirings which are connected to the lower electrode and the upper electrode through via plugs. A plane of the upper electrode is made rectangular. The lower layer wirings are not arranged right below one or more than one edge of the plane of the upper electrode. | 12-02-2010 |