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Itskovich

Alexander Itskovich, Yoqneam Ilit IL

Patent application number	Description	Published
20090013289	CIRCUIT DESIGN OPTIMIZATION OF INTEGRATED CIRCUIT BASED CLOCK GATED MEMORY ELEMENTS - A novel method for optimizing the design of digital circuits containing clock gated memory elements. The method unclock gates memory elements by adding necessary feedback loops. Logic functions of memory element outputs in the circuit are viewed as a whole, rather than as separate functions for each input. Detection of duplicate unclock gated memory elements is then effected by identifying identical danonical representations of said unclock gated memory elements. Identified duplicate clock gated memory elements can then be eliminated from the original digital circuit. Further optimization can be accomplished by applying standard logic optimization algorithms to all unclock gated memory elements in said digital circuit. The resulting optimized circuit is clock gated and replaces the original clock gated circuit in said digital circuit.	01-08-2009
20090044154	OVER APPROXIMATION OF INTEGRATED CIRCUIT BASED CLOCK GATING LOGIC - A novel method for optimizing the implementation of clock gating logic in digital circuits utilizing clock gating. The method over-approximates the clock gating function by removing the variable with the least influence on the resulting approximation function. Approximations of clock gating functions expressed in normal form are performed by removing an appropriate component from the function. Approximations of clock gating functions expressed in conjunctive normal form are performed by removing a clause from the function. Approximations of clock gating functions expressed in disjunctive normal form are performed by removing a literal from a clause in the function.	02-12-2009

Alexander Itskovich, Yokneam Llit IL

Patent application number	Description	Published
20080301604	APPARATUS FOR AND METHOD OF ESTIMATING THE QUALITY OF CLOCK GATING SOLUTIONS FOR INTEGRATED CIRCUIT DESIGN - A novel apparatus for and method of estimating the quality of candidate clock gating solutions. The quality estimation mechanism of the present invention filters candidate clock gating solutions by estimating a measure of the quality of each candidate solution. The effect of the proposed solution on both timing and leakage power is considered by determining the intersection coefficient for each candidate clock gating solution. The intersection coefficient (IC) is the number of signals shared by both the data logic portion and clock enable logic portions of a proposed clock gating solution. Only those proposed solutions whose IC value is less than or equal to a threshold are considered as possible clock gating solutions. The IC value functions as a reliable predictor of whether a candidate clock gating solution is a good solution without requiring complex heavy analyses that would normally be applied to the final circuit design.	12-04-2008

Mikhail Itskovich, Columbia, MD US

Patent application number	Description	Published
20090122913	System and method for controlling modulation - A system and method for controlling modulation. The system includes a plurality of modulators and a transmitting unit. The plurality of modulators decodes data from a data signal and also encodes the data into a clock signal. The transmitting unit transmits the encoded clock signal. According to the system and method disclosed herein, the present invention provides optimized coding efficiency while minimizing overall power consumption.	05-14-2009