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Itay Peled
Itay Peled, Herzelia IL
| Patent application number | Description | Published |
|---|---|---|
| 20110040912 | APPARATUS AND METHOD FOR MULTIPLE ENDIAN MODE BUS MATCHING - Apparatus and method for bus matching. The method includes: receiving data transfer characteristics at a first endian mode and at a second endian mode; determining a connectivity of multiple devices to an interfacing bus in response to the data transfer characteristics and in response to a relationship between a width of the interfacing bus and a width of each device interface; wherein at least one device interface is connected in parallel to multiple interfacing bus portions; and configuring a control logic such as to provide control signals representative of a transfer of data over the interfacing bus; whereas the control logic is configured in response to the connectivity. The apparatus includes: an interfacing bus characterized by an interfacing bus width; a master device, connected to the interfacing bus, whereas the master device includes a master device interface; multiple slave devices, each slave device connected to the interfacing bus and includes a slave device interface; wherein at least one slave device interface is connected in parallel to multiple interfacing bus portions; and control logic, connected to the interfacing bus and to the master device, the control logic is adapted to provide control signals representative of a transfer of data over the interfacing bus; whereas the control logic is configured in response to a connectivity of the multiple slave devices to the interfacing bus; whereas said connectivity is responsive to data transfer characteristics and is responsive to relationships between a width of the interfacing bus and a width of each device interface. | 02-17-2011 |
Itay Peled, Beer-Shev A IL
| Patent application number | Description | Published |
|---|---|---|
| 20110022800 | SYSTEM AND A METHOD FOR SELECTING A CACHE WAY - A method for selecting a cache way, the method includes: selecting an initially selected cache way out of multiple cache ways of a cache module for receiving a data unit; the method being characterized by including: searching, if the initially selected cache way is locked, for an unlocked cache way, out of at least one group of cache ways that are located at predefined offsets from the first cache way. | 01-27-2011 |
Itay Peled, Herzelia IT
| Patent application number | Description | Published |
|---|---|---|
| 20100325366 | SYSTEM AND METHOD FOR FETCHING AN INFORMATION UNIT - A device and a method for fetching an information unit, the method includes: receiving a request to execute a write through cacheable operation of the information unit; emptying a fetch unit from data, wherein the fetch unit is connected to a cache module and to a high level memory unit; determining, when the fetch unit is empty, whether the cache module stores an older version of the information unit; and selectively writing the information unit to the cache module in response to the cache module in response to the determination. | 12-23-2010 |
Itay Peled, Beer-Sheva IL
| Patent application number | Description | Published |
|---|---|---|
| 20080301371 | Memory Cache Control Arrangement and a Method of Performing a Coherency Operation Therefor - A memory cache control arrangement for performing a coherency operation on a memory cache comprises a receive processor for receiving an address group indication for an address group comprising a plurality of addresses associated with a main memory. The address group indication may indicate a task identity and an address range corresponding to a memory block of the main memory. A control unit processes each line of a group of cache lines sequentially. Specifically it is determined if each cache line is associated with an address of the address group by evaluating a match criterion. If the match criterion is met, a coherency operation is performed on the cache line. If a conflict exists between the coherency operation and another memory operation the coherency means inhibits the coherency operation. The invention allows a reduced duration of a cache coherency operation. The duration is further independent of the size of the main memory address space covered by the coherency operation. | 12-04-2008 |
| 20090063779 | CACHE MEMORY AND A METHOD FOR SERVICING ACCESS REQUESTS - A cache memory that includes: (i) an arbitrator, connected to multiple access generator, the arbitrator is adapted to receive different types of access requests from the multiple access generators and to select a single access request per arbitration cycle; (ii) a sequence of pipeline stages, the sequence comprises an input pipeline stage that is connected to the arbiter; and (iii) multiple cache resources, connected to the sequence of pipeline stages; wherein each cache resource can be read only by a small portion of the sequence of pipeline stages and can be written to only by a small portion of the sequence of pipeline stages. | 03-05-2009 |
| 20100122037 | DEVICE AND METHOD FOR GENERATING CACHE USER INITIATED PRE-FETCH REQUESTS - A method for generating cache user initiated pre-fetch requests, the method comprises initiating a sequence of user initiated pre-fetch requests; the method being characterized by: determining the timing of user initiated pre-fetch requests of the sequence of user initiated pre-fetch requests in response to: the timing of an occurrence of a last triggering event, a user initiated pre-fetch sequence delay period and a user initiated pre-fetch sequence rate. | 05-13-2010 |
Itay Peled, Hod Hasharon IL
| Patent application number | Description | Published |
|---|---|---|
| 20100030974 | SYSTEM AND METHOD FOR FETCHING INFORMATION TO A CACHE MODULE USING A WRITE BACK ALLOCATE ALGORITHM - A write back allocate system that includes: (i) a store request circuit; (ii) a processor, adapted to generate a store request that comprises an information unit and an information unit address; and (iii) a cache module, connected to the store request circuit and to a high level memory unit. A single cache module line includes multiple segments, each segment is adapted to store a single information unit. A content of a cache module line is retrieved from the high level memory unit by generating a fetch burst that includes multiple segment fetch operations. The store request circuit includes a snooper and a controller. The snooper detects a portion of an address of a cache segment of a cache line that is being fetched during a fetch burst. The controller is adapted to request from the cache module to receive the information unit before a completion of the fetch burst if the portion of the address of the cache segment matches a corresponding portion of the information unit address. | 02-04-2010 |
| 20100049939 | METHOD FOR ADDRESS COMPARISON AND A DEVICE HAVING ADDRESS COMPARISON CAPABILITIES - A method for address comparison, the method includes: (i) receiving an input address; (ii) determining whether the input address is within a memory segment out of a group of memory segments by comparing, in parallel, the input address to memory segment boundaries of each memory segment of the group; (iii) wherein a comparison between the input address and a memory segment boundary comprises: (a) applying a XOR operation on bits of a most significant portion of the input address and corresponding bits of a most significant portion of the memory segment boundary; (b) ignoring bits of a least significant portion of the input address and corresponding bits of a least significant portion of the memory segment boundary; and (c) comparing, by utilizing a set of full comparators, between bits of an intermediate portion of the input address and corresponding bits of an intermediate portion of the memory segment boundary; wherein a location of bits that form the intermediate portion of the input address and of the memory segment boundary is selected in response to an alignment restriction imposed on the memory segment, to a size of the memory segment and in response to a boundary restriction imposed on the memory segment. | 02-25-2010 |