| Patent application number | Description | Published |
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| 20080304174 | OPTIMIZING TAPE SPEED FOR A SYNC OPERATION - Provided are techniques for determining a tape speed for a next sync operation. A sync command is received. An average transaction size and an average host transfer rate of a set of previous sync operations are calculated. The tape speed for the next sync operation is determined using the average transaction size, the average host transfer rate, and a backhitch time. Data is written to a tape cartridge using the determined tape speed. | 12-11-2008 |
| 20100278760 | Cosmetics - The cosmetic of the present invention is a cosmetic that alleviates skin irritation by blending in polypropylene glycol, a specific polar oil, or polybutylene glycol, as well as an ultraviolet absorbent. The present invention also relates to an agent and a method for alleviating irritation by lipophilic drugs. Since the present invention alleviates skin irritation due to ultraviolet absorbents and lipophilic drugs in cosmetics, any amount of ultraviolet absorbents and lipophilic drugs can be blended in cosmetics, and therefore cosmetics that can fully manifest their effects can be provided. Also, it is possible to prepare a safe sunblock cosmetic with superior ultraviolet protection effects because the ultraviolet absorbent is not absorbed through skin. | 11-04-2010 |
| 20110122522 | Tape Recorder And Tape Recording That Increases Empty Tape Area Without Loss of Necessary Data - Provided is a tape recorder that has a tape including at least one partition and that controls access to the tape. The tape recorder includes: means for identifying a position of data on the tape; means for sequentially reading necessary data areas in the data; means for sequentially copying the necessary data areas to the beginning of an empty area on the tape; means for creating a continuous front empty area formed of unnecessary data areas and copy source areas of the necessary data areas on the tape; and means for moving a beginning of the partition (BOP) to a position immediately after the front empty area and for updating the position information on the beginning of the partition. | 05-26-2011 |
| Patent application number | Description | Published |
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| 20090190391 | MAGNETORESISTIVE RANDOM ACCESS MEMORY - A word line voltage is applied to a plurality of word lines. A read/write voltage is applied to a plurality of bit lines. The read/write voltage is applied to a plurality of source lines. A word line selector selects the word line and applies the word line voltage. A driver applies a predetermined voltage to the bit line and the source line, thereby supplying a current to the memory cell. A read circuit reads a first current having flowed through the memory cell, and determines data stored in the memory cell. When performing the read, the driver supplies a second current to second bit lines among other bit lines, which are adjacent to the first bit line through which the first current has flowed. The second current generates a magnetic field in a direction to suppress a write error in the memory cell from which data is to be read. | 07-30-2009 |
| 20090257274 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes n resistance change elements which are arranged in one cell, have a low-resistance state and a high resistance state, are connected in series or parallel, have different resistance values in the same resistance state, and change between the low-resistance state and the high-resistance state under different conditions, and a write circuit which is connected to one end of the n resistance change elements, and applies a pulse current m (1≦m≦n) times to the n resistance change elements during a write operation. Letting Im be a current value of an mth pulse current, condition I | 10-15-2009 |
| 20100165701 | RESISTIVE MEMORY - A resistive memory includes a plurality of memory cells, a plurality of reference cells having mutually different resistance values, at least one sense amplifier having a first input terminal connected to one selected memory cell which is selected from the plurality of memory cells at a time of read, and a second input terminal connected to one selected reference cell which is selected from the plurality of reference cells at the time of read, and one latch circuit which holds offset information of the at least one sense amplifier. The resistive memory further includes a decoder which selects, in accordance with the offset information, the one selected reference cell from the plurality of reference cells, and connects the one selected reference cell to the second input terminal of the at least one sense amplifier. | 07-01-2010 |
| 20100172189 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - A non-volatile semiconductor storage device includes: a memory string including a plurality of memory cells connected in series; a first selection transistor having one end connected to one end of the memory string; a first wiring having one end connected to the other end of the first selection transistor; a second wiring connected to a gate of the first selection transistor. A control circuit is configured to boost voltages of the second wiring and the first wiring in the erase operation, while keeping the voltage of the first wiring greater than the voltage of the second wiring by a certain potential difference. The certain potential difference is a potential difference that causes a GIDL current. | 07-08-2010 |
| 20100214838 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - A non-volatile semiconductor storage device includes a control circuit performing an erase operation to erase data from a selected one of memory transistors. The control circuit applies a first voltage to the other end of selected one of selection transistors, causes the selected one of the selection transistors to turn on, and causes any one of the memory transistors to turn on that is closer to the selection transistor than the selected one of the memory transistors. The control circuit also applies a second voltage lower than the first voltage to a gate of the selected one of the memory transistors. Such a potential difference between the first voltage and the second voltage causing a change in electric charges in the electric charge storage layer. | 08-26-2010 |
