| Patent application number | Description | Published |
|---|
| 20080237882 | Annular via drilling (AVD) technology - In some embodiments, annular via drilling (AVD) technology is presented. In this regard, an annular via is introduced comprising an inner wall and an outer wall, the inner wall and the outer wall coupled with a dielectric layer and extending linearly from a surface of a conductor to a top of the dielectric layer. Other embodiments are also disclosed and claimed. | 10-02-2008 |
| 20090001550 | Method of Forming a Multilayer Substrate Core Structure Using Sequential Microvia Laser Drilling And Substrate Core Structure Formed According to the Method - A method of fabricating a substrate core structure, and a substrate core structure formed according to the method. The method includes: laser drilling a first set of via openings through a starting insulating layer; filling the first set of via openings with a conductive material to provide a first set of conductive vias; providing first and second patterned conductive layers on opposite sides of the starting insulating layer; providing a supplemental insulating layer onto the first patterned conductive layer; laser drilling a second set of via openings through the supplemental insulating layer; filling the second set of via openings with a conductive material to provide a second set of conductive vias; and providing a supplemental patterned conductive layer onto an exposed side of the supplemental insulating layer, the second set of conductive vias contacting the first patterned conductive layer and the supplemental patterned conductive layer at opposite sides thereof. | 01-01-2009 |
| 20090002958 | Method of Forming a Substrate Core Structure Using Microvia Laser Drilling and Conductive Layer Pre-Patterning And Substrate Core Structure Formed According to the Method - A method of fabricating a substrate core structure comprises, providing first and second patterned conductive layers defining openings therein on each side of a starting insulating layer; providing a first and a second supplemental insulating layers onto respective ones of a first and a second patterned conductive layer; laser drilling a set of via openings extending through at least some of the conductive layer openings of the first and second patterned conductive layers; filling the set of via openings with a conductive material to provide a set of conductive vias; and providing a first and a second supplemental patterned conductive layer onto respective ones of the first and the second supplemental insulating layers, the set of conductive vias contacting the first supplemental patterned conductive layer at one side thereof and the second supplemental patterned conductive layer at another side thereof. | 01-01-2009 |
| 20090056989 | PRINTED CIRCUIT BOARD AND METHOD FOR PREPARATION THEREOF - Disclosed is a method for preparing a printed circuit board. The method comprises forming a conductive layer on an insulated layer substrate. The method further includes partitioning the conductive layer into a first area and a second area by applying a photoresist mask. Furthermore, the method includes applying a first etching process to the conductive layer to pattern a first set of features on the first area of the conductive layer. Thereafter, the method includes applying a second etching process to the conductive layer to pattern a second set of features on the second area of the conductive layer. The second set of features on the second area of the conductive layer has a finer pitch as compared to the first set of features on the first area of the conductive layer. | 03-05-2009 |
| 20090084755 | METHOD FOR FORMING MICRO-VIAS ON A SUBSTRATE - A method for forming at least one micro-via on a substrate is disclosed. The method comprises drilling at least one hole in a substrate by using a first laser beam. The first laser beam has an energy distribution, which is more at edges of the first laser beam than at the center of the first laser beam. The method further comprises forming at least one blank pattern on a top surface of the substrate and around an outer periphery of the at least one hole by removing at least a portion of the substrate by using a second laser beam. At least one blank pattern of the plurality of blank pattern corresponds to pad of the at least one micro-via. Thereafter, the method comprises filling the plurality of blank patterns and the at least one micro-via with a conductive material to form at least micro-via. | 04-02-2009 |
| 20090108455 | INTEGRATED CIRCUIT AND PROCESS FOR FABRICATING THEREOF - A process for fabricating an Integrated Circuit (IC) and the IC formed thereby is disclosed. The process comprises providing a substrate. The process further comprises forming a plurality of longitudinal trenches in the substrate and depositing a layer of a first conductive material on at least one longitudinal trench of the plurality of longitudinal trenches. A first layer of a second conductive material is deposited on the layer of the first conductive material. Thereafter, the process includes depositing a second layer of the second conductive material on the first layer of the second conductive material. The second layer of the second conductive material at least partially fills the at least one longitudinal trench. The first conductive material is selected such that a reduction potential of the first conductive material is less than a reduction potential of the second conductive material. | 04-30-2009 |
| 20090166320 | SELECTIVE ELECTROLESS PLATING FOR ELECTRONIC SUBSTRATES - In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including forming a film on a surface of a substrate, the film designed to prevent the seeding of an electroless plating catalyst, laser ablating the surface of the substrate through the film to form trenches, and seeding the surface of the substrate with an electroless plating catalyst. Other embodiments are also disclosed and claimed. | 07-02-2009 |
| 20090238233 | OPTICAL DIE STRUCTURES AND ASSOCIATED PACKAGE SUBSTRATES - Optical die structures and associated package substrates are generally described. In one example, an electronic device includes a package substrate having a package substrate core, a dielectric layer coupled with the package substrate core, and one or more input/output (I/O) optical fibers coupled with the package substrate core or coupled with the build-up dielectric layer, or combinations thereof, the one or more I/O optical fibers to guide I/O optical signals to and from the package substrate wherein the one or more I/O optical fibers allow both input and output optical signals to travel through the one or more I/O optical fibers. | 09-24-2009 |
| 20090238516 | SUBSTRATES FOR OPTICAL DIE STRUCTURES - Package substrates for optical die structures are generally described. In one example, an apparatus includes a package substrate having one or more plated through hole (PTH) structures, an optical waveguide coupled with the package substrate, the optical waveguide having one or more input/output (I/O) optical signal pathways to route I/O signals to and from the package substrate, and one or more optical fibers coupled with the optical waveguide, the one or more optical fibers being disposed in the PTH structures to route I/O signals to and from a motherboard. | 09-24-2009 |
| 20100044862 | METHOD OF FORMING COLLAPSE CHIP CONNECTION BUMPS ON A SEMICONDUCTOR SUBSTRATE - A method of forming collapse chip connection bumps on a semiconductor substrate is provided. The method includes providing a semiconductor substrate having a plurality of bump vias on a top surface of the semiconductor substrate and electroplating the plurality of bump vias to form a plurality of via pads on the top surface of the semiconductor substrate. The method also includes disposing a plurality of solder microballs on the top surface of the semiconductor substrate, wherein each solder microball is placed on a corresponding via pad on the semiconductor substrate and reflowing the plurality of solder microballs to form the collapse chip connection bumps on the semiconductor substrate. | 02-25-2010 |
| 20100126009 | Method of enabling selective area plating on a substrate - A method of enabling selective area plating on a substrate ( | 05-27-2010 |
| 20100163535 | Method of forming a pattern on a work piece, method of shaping a beam of electromagnetic radiation for use in said method, and aperture for shaping a beam of electromagnetic radiation - A method of forming a pattern ( | 07-01-2010 |
| 20110018145 | MICROELECTRONIC SUBSTRATE INCLUDING EMBEDDED COMPONENTS AND SPACER LAYER AND METHOD OF FORMING SAME - A microelectronic substrate, a method of forming the same, and a system including the same. The microelectronic substrate comprises: a conductive layer; a spacer layer disposed onto the conductive dielectric layer; a dielectric build-up layer disposed onto the spacer layer, the spacer layer being made of a material that has a lower shrinkage than a material of the embedding dielectric-build-up layer during curing, and a higher viscosity than a material of the embedding dielectric build-up layer in its pre-cure form and during curing; and active or passive microelectronic components embedded within the dielectric build-up layer. | 01-27-2011 |
| 20110058340 | METHOD OF FORMING A MULTILAYER SUBSTRATE CORE STRUCTURE USING SEQUENTIAL MICROVIA LASER DRILLING AND SUBSTRATE CORE STRUCTURE FORMED ACCORDING TO THE METHOD - A method of fabricating a substrate core structure, and a substrate core structure formed according to the method. The method includes: laser drilling a first set of via openings through a starting insulating layer; filling the first set of via openings with a conductive material to provide a first set of conductive vias; providing first and second patterned conductive layers on opposite sides of the starting insulating layer; providing a supplemental insulating layer onto the first patterned conductive layer; laser drilling a second set of via openings through the supplemental insulating layer; filling the second set of via openings with a conductive material to provide a second set of conductive vias; and providing a supplemental patterned conductive layer onto an exposed side of the supplemental insulating layer, the second set of conductive vias contacting the first patterned conductive layer and the supplemental patterned conductive layer at opposite sides thereof. | 03-10-2011 |
