Patent application number | Description | Published |
20090047783 | METHOD OF REMOVING UNWANTED PLATED OR CONDUCTIVE MATERIAL FROM A SUBSTRATE, AND METHOD OF ENABLING METALLIZATION OF A SUBSTRATE USING SAME - A method of removing unwanted material from a substrate includes providing a system ( | 02-19-2009 |
20090081381 | METHOD OF ENABLING SELECTIVE AREA PLATING ON A SUBSTRATE - A method of enabling selective area plating on a substrate includes forming a first electrically conductive layer ( | 03-26-2009 |
20090152743 | ROUTING LAYER FOR A MICROELECTRONIC DEVICE, MICROELECTRONIC PACKAGE CONTAINING SAME, AND METHOD OF FORMING A MULTI-THICKNESS CONDUCTOR IN SAME FOR A MICROELECTRONIC DEVICE - A routing layer for a microelectronic device includes a first region ( | 06-18-2009 |
20110034002 | SYSTEMS AND METHODS TO LAMINATE PASSIVES ONTO SUBSTRATE - A method may include depositing a dielectric layer onto a substrate, removing portions of the dielectric layer to create a plurality of separated non-removed portions of the dielectric layer, depositing one or more passive electronic components into each of the plurality of separated non-removed portions, and curing the separated non-removed portions of the dielectric layer. | 02-10-2011 |
20110123725 | METHOD OF ENABLING SELECTIVE AREA PLATING ON A SUBSTRATE - A method of enabling selective area plating on a substrate includes forming a first electrically conductive layer ( | 05-26-2011 |
20110147929 | THROUGH MOLD VIA POLYMER BLOCK PACKAGE - Methods for forming an integrated circuit chip package having through mold vias in a polymer block, and such packages are described. For example, a first interconnect layer may be formed on a molded polymer block, wherein the first interconnect layer comprises first interconnects through a first polymer layer and to the block. Then, at least one second interconnect layer may be formed on the first interconnect layer, wherein the second interconnect layer comprises second interconnects through a second polymer layer and to the first interconnects of the first interconnect layer. Through mold vias may then be formed through the block, into the first interconnect layer, and to the first interconnects. The through mold vias may be filled with solder to form bumps contacting the first interconnects and extending above the block. Other embodiments are also described and claimed. | 06-23-2011 |
20110211249 | Optical device and method of making - An optical device and method is disclosed for forming the optical device within the wide-bandgap semiconductor substrate. The optical device is formed by directing a thermal energy beam onto a selected portion of the wide-bandgap semiconductor substrate for changing an optical property of the selected portion to form the optical device in the wide-bandgap semiconductor substrate. The thermal energy beam defines the optical and physical properties of the optical device. The optical device may take the form of an electro-optical device with the addition of electrodes located on the wide-bandgap semiconductor substrate in proximity to the optical device for changing the optical property of the optical device upon a change of a voltage applied to the optional electrodes. The invention is also incorporated into a method of using the optical device for remotely sensing temperature, pressure and/or chemical composition. | 09-01-2011 |
20110304018 | LOW TEMPERATURE DEPOSITION AND ULTRA FAST ANNEALING OF INTEGRATED CIRCUIT THIN FILM CAPACITOR - Some embodiments of the invention include thin film capacitors formed on a package substrate of an integrated circuit package. At least one of the film capacitors includes a first electrode layer, a second electrode layer, and a dielectric layer between the first and second electrode layers. Each of the first and second electrode layers and the dielectric layer is formed individually and directly on the package substrate. Other embodiments are described and claimed. | 12-15-2011 |
20120161330 | DEVICE PACKAGING WITH SUBSTRATES HAVING EMBEDDED LINES AND METAL DEFINED PADS - Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing. | 06-28-2012 |
20120299179 | THROUGH MOLD VIA POLYMER BLOCK PACKAGE - Methods for forming an integrated circuit chip package having through mold vias in a polymer block, and such packages are described. For example, a first interconnect layer may be formed on a molded polymer block, wherein the first interconnect layer comprises first interconnects through a first polymer layer and to the block. Then, at least one second interconnect layer may be formed on the first interconnect layer, wherein the second interconnect layer comprises second interconnects through a second polymer layer and to the first interconnects of the first interconnect layer. Through mold vias may then be farmed through the block, into the first interconnect layer, and to the first interconnects. The through mold vias may be filled with solder to form bumps contacting the first interconnects and extending above the block. Other embodiments are also described and claimed. | 11-29-2012 |
20140004361 | SUBSTRATE CORES FOR LASER THROUGH HOLE FORMATION | 01-02-2014 |
20140061927 | CHIP PACKAGE INCORPORATING INTERFACIAL ADHESION THROUGH CONDUCTOR SPUTTERING - This disclosure relates generally to an electronic device and method having can include a method of making a chip package. An insulator layer comprising an insulator material, the insulator layer positioned with respect to a first conductive line, forming a second conductive line with respect to the insulator layer, wherein the insulator layer is positioned between the first conductive line and the second conductive line, forming a opening in the insulator layer between the first conductive line and the second conductive line, at least some of the insulator material within the opening being exposed, and chemically bonding a conductor to the at least some of the insulator material within the opening, wherein the conductor electrically couples the first conductive line to the second conductive line. | 03-06-2014 |
20140168032 | ARCHITECTURE FOR SEAMLESS INTEGRATED DISPLAY SYSTEM - Embodiments of systems and methods of seamless displays are generally described herein. In some embodiments, a backpanel device comprising display drive circuitry can be removably coupled with a display device via an array of contact members. The display device can include image-producing elements or pixels that can be selectively driven by the backpanel device via corresponding portions of the array of contact members. Multiple display devices can be disposed adjacently on one or more backpanel devices such that an image displayed across the multiple display devices appears seamless. | 06-19-2014 |
20140168263 | CONSUMER ELECTRONICS WITH AN INVISIBLE APPEARANCE - A method, electronic device and system for displaying background images on an electronic device, wherein the electronic device includes a face that has at least one edge and a display visible in the face. The display extends to at least one edge of the face. Furthermore, a processor is coupled to the display and a photosensor is coupled to the processor. The photosensor is configured to capture background images of a background obscured behind the device when viewing the device face. The processor is configured to composite the background image with a second image. | 06-19-2014 |
20140204454 | CONFIGURATION OF ACOUSTO-OPTIC DEFLECTORS FOR LASER BEAM SCANNING - A first acousto-optic deflector receives a laser beam. The first acousto-optic deflector diffracts the received laser beam along a first axis. A second acousto-optic deflector receives the diffracted laser beam. The second acousto-optic deflector diffracts the received diffracted laser beam along a second axis. | 07-24-2014 |
20140321091 | PACKAGE SUBSTRATE WITH HIGH DENSITY INTERCONNECT DESIGN TO CAPTURE CONDUCTIVE FEATURES ON EMBEDDED DIE - Embodiments of the present disclosure are directed towards techniques and configurations for interconnect structures embedded in a package assembly including a bridge. In one embodiment, a package assembly may include a package substrate, a bridge embedded in the package substrate and including a bridge substrate, and an interconnect structure including a via extending through the package substrate into a surface of the bridge substrate and configured to interface with a conductive feature disposed on or beneath the surface of the bridge substrate. The interconnect structure may be configured to route electrical signals between the conductive feature and a die mounted on the package substrate. Other embodiments may be described and/or claimed. | 10-30-2014 |
20150014852 | PACKAGE ASSEMBLY CONFIGURATIONS FOR MULTIPLE DIES AND ASSOCIATED TECHNIQUES - Embodiments of the present disclosure are directed towards package assembly configurations for multiple dies and associated techniques. In one embodiment, a package assembly includes a package substrate having a first side and a second side disposed opposite to the first side, a first die mounted on the first side and electrically coupled with the package substrate by one or more first die-level interconnects, a second die mounted on the second side and electrically coupled with the package substrate by one or more second die-level interconnects and package-level interconnect structures disposed on the first side of the package substrate and configured to route electrical signals between the first die and an electrical device external to the package substrate and between the second die and the external device. Other embodiments may be described and/or claimed. | 01-15-2015 |
20150021778 | CHIP PACKAGE INCORPORATING INTERFACIAL ADHESION THROUGH CONDUCTOR SPUTTERING - This disclosure relates generally to an electronic device and method having can include a method of making a chip package. An insulator layer comprising an insulator material, the insulator layer positioned with respect to a first conductive line, forming a second conductive line with respect to the insulator layer, wherein the insulator layer is positioned between the first conductive line and the second conductive line, forming a opening in the insulator layer between the first conductive line and the second conductive line, at least some of the insulator material within the opening being exposed, and chemically bonding a conductor to the at least some of the insulator material within the opening, wherein the conductor electrically couples the first conductive line to the second conductive line. | 01-22-2015 |
20150048515 | FABRICATION OF A SUBSTRATE WITH AN EMBEDDED DIE USING PROJECTION PATTERNING AND ASSOCIATED PACKAGE CONFIGURATIONS - Embodiments of the present disclosure are directed towards techniques and configurations for using projection patterning in making an electronic substrate with an embedded die. In one embodiment, a method may include providing a die embedded in dielectric material of a substrate, and projecting a laser beam through a mask with a preconfigured pattern to create a projected mask pattern on a surface of the dielectric material in accordance with the preconfigured pattern. The projected mask pattern may include a via disposed over the die. Other embodiments may be described and/or claimed. | 02-19-2015 |