| Patent application number | Description | Published |
|---|
| 20090047783 | METHOD OF REMOVING UNWANTED PLATED OR CONDUCTIVE MATERIAL FROM A SUBSTRATE, AND METHOD OF ENABLING METALLIZATION OF A SUBSTRATE USING SAME - A method of removing unwanted material from a substrate includes providing a system ( | 02-19-2009 |
| 20090081381 | METHOD OF ENABLING SELECTIVE AREA PLATING ON A SUBSTRATE - A method of enabling selective area plating on a substrate includes forming a first electrically conductive layer ( | 03-26-2009 |
| 20090152743 | ROUTING LAYER FOR A MICROELECTRONIC DEVICE, MICROELECTRONIC PACKAGE CONTAINING SAME, AND METHOD OF FORMING A MULTI-THICKNESS CONDUCTOR IN SAME FOR A MICROELECTRONIC DEVICE - A routing layer for a microelectronic device includes a first region ( | 06-18-2009 |
| 20110034002 | SYSTEMS AND METHODS TO LAMINATE PASSIVES ONTO SUBSTRATE - A method may include depositing a dielectric layer onto a substrate, removing portions of the dielectric layer to create a plurality of separated non-removed portions of the dielectric layer, depositing one or more passive electronic components into each of the plurality of separated non-removed portions, and curing the separated non-removed portions of the dielectric layer. | 02-10-2011 |
| 20110123725 | METHOD OF ENABLING SELECTIVE AREA PLATING ON A SUBSTRATE - A method of enabling selective area plating on a substrate includes forming a first electrically conductive layer ( | 05-26-2011 |
| 20110147929 | THROUGH MOLD VIA POLYMER BLOCK PACKAGE - Methods for forming an integrated circuit chip package having through mold vias in a polymer block, and such packages are described. For example, a first interconnect layer may be formed on a molded polymer block, wherein the first interconnect layer comprises first interconnects through a first polymer layer and to the block. Then, at least one second interconnect layer may be formed on the first interconnect layer, wherein the second interconnect layer comprises second interconnects through a second polymer layer and to the first interconnects of the first interconnect layer. Through mold vias may then be formed through the block, into the first interconnect layer, and to the first interconnects. The through mold vias may be filled with solder to form bumps contacting the first interconnects and extending above the block. Other embodiments are also described and claimed. | 06-23-2011 |
| 20110211249 | Optical device and method of making - An optical device and method is disclosed for forming the optical device within the wide-bandgap semiconductor substrate. The optical device is formed by directing a thermal energy beam onto a selected portion of the wide-bandgap semiconductor substrate for changing an optical property of the selected portion to form the optical device in the wide-bandgap semiconductor substrate. The thermal energy beam defines the optical and physical properties of the optical device. The optical device may take the form of an electro-optical device with the addition of electrodes located on the wide-bandgap semiconductor substrate in proximity to the optical device for changing the optical property of the optical device upon a change of a voltage applied to the optional electrodes. The invention is also incorporated into a method of using the optical device for remotely sensing temperature, pressure and/or chemical composition. | 09-01-2011 |
| 20110304018 | LOW TEMPERATURE DEPOSITION AND ULTRA FAST ANNEALING OF INTEGRATED CIRCUIT THIN FILM CAPACITOR - Some embodiments of the invention include thin film capacitors formed on a package substrate of an integrated circuit package. At least one of the film capacitors includes a first electrode layer, a second electrode layer, and a dielectric layer between the first and second electrode layers. Each of the first and second electrode layers and the dielectric layer is formed individually and directly on the package substrate. Other embodiments are described and claimed. | 12-15-2011 |
