Patent application number | Description | Published |
20090065876 | Metal High-K Transistor Having Silicon Sidewall for Reduced Parasitic Capacitance, and Process to Fabricate Same - A method is disclosed to reduce parasitic capacitance in a metal high dielectric constant (MHK) transistor. The method includes forming a MHK gate stack upon a substrate, the MHK gate stack having a bottom layer of high dielectric constant material, a middle layer of metal, and a top layer of one of amorphous silicon or polycrystalline silicon. The method further forms a depleted sidewall layer on sidewalls of the MHK gate stack so as to overlie the middle layer and the top layer, and not the bottom layer. The depleted sidewall layer is one of amorphous silicon or polycrystalline silicon. The method further forms an offset spacer layer over the depleted sidewall layer and over exposed surfaces of the bottom layer. | 03-12-2009 |
20090273041 | TRANSISTOR WITH HIGH-K DIELECTRIC SIDEWALL SPACER - A transistor is provided that includes a silicon layer including a source region and a drain region, a gate stack disposed on the silicon layer between the source region and the drain region, and a sidewall spacer disposed on sidewalls of the gate stack. The gate stack includes a first layer of high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. The sidewall spacer includes a high dielectric constant material and covers the sidewalls of at least the second and third layers of the gate stack. Also provided is a method for fabricating such a transistor. | 11-05-2009 |
20090273042 | METAL HIGH DIELECTRIC CONSTANT TRANSISTOR WITH REVERSE-T GATE - A transistor is provided. The transistor includes a silicon layer including a source region and a drain region. A gate stack is disposed on the silicon layer between the source region and the drain region. The gate stack comprises a first layer of a high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. A lateral extent of the second layer of the gate stack is substantially greater than a lateral extent of the third layer of the gate stack. Also provided are methods for fabricating such a transistor. | 11-05-2009 |
20090275182 | METHOD FOR FABRICATING A METAL HIGH DIELECTRIC CONSTANT TRANSISTOR WITH REVERSE-T GATE - A method is provided for fabricating a transistor. A silicon layer is provided, and a first layer comprising a high dielectric constant material is formed on the silicon layer. A second layer including a metal or metal alloy is formed on the first layer, and a third layer including silicon or polysilicon is formed on the second layer. The first, second, and third layers are etched so as to form a gate stack, and ions are implanted to form source and drain regions in the silicon layer. Source and drain silicide contact areas are formed in the source and drain regions, and a gate silicide contact area is formed in the third layer. After forming these silicide contact areas, the third layer is etched without etching the first and second layers, so as to substantially reduce the width of the third layer. | 11-05-2009 |
20090298275 | Metal High-K Transistor Having Silicon Sidewall For Reduced Parasitic Capacitance, And Process To Fabricate Same - A method is disclosed to reduce parasitic capacitance in a metal high dielectric constant (MHK) transistor. The method includes forming a MHK gate stack upon a substrate, the MHK gate stack having a bottom layer of high dielectric constant material, a middle layer of metal, and a top layer of one of amorphous silicon or polycrystalline silicon. The method further forms a depleted sidewall layer on sidewalls of the MHK gate stack so as to overlie the middle layer and the top layer, and not the bottom layer. The depleted sidewall layer is one of amorphous silicon or polycrystalline silicon. The method further forms an offset spacer layer over the depleted sidewall layer and over exposed surfaces of the bottom layer. | 12-03-2009 |
20090302400 | METAL HIGH DIELECTRIC CONSTANT TRANSISTOR WITH REVERSE-T GATE - A transistor is provided. The transistor includes a silicon layer including a source region and a drain region. A gate stack is disposed on the silicon layer between the source region and the drain region. The gate stack comprises a first layer of a high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. A lateral extent of the second layer of the gate stack is substantially greater than a lateral extent of the third layer of the gate stack. Also provided are methods for fabricating such a transistor. | 12-10-2009 |
20090307635 | METAL HIGH DIELECTRIC CONSTANT TRANSISTOR WITH REVERSE-T GATE - A transistor is provided. The transistor includes a silicon layer including a source region and a drain region. A gate stack is disposed on the silicon layer between the source region and the drain region. The gate stack comprises a first layer of a high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. A lateral extent of the second layer of the gate stack is substantially greater than a lateral extent of the third layer of the gate stack. Also provided are methods for fabricating such a transistor. | 12-10-2009 |
20100006956 | Metal High-K Transistor Having Silicon Sidewall For Reduced Parasitic Capacitance, And Process To Fabricate Same - A method is disclosed to reduce parasitic capacitance in a metal high dielectric constant (MHK) transistor. The method includes forming a MHK gate stack upon a substrate, the MHK gate stack having a bottom layer of high dielectric constant material, a middle layer of metal, and a top layer of one of amorphous silicon or polycrystalline silicon. The method further forms a depleted sidewall layer on sidewalls of the MHK gate stack so as to overlie the middle layer and the top layer, and not the bottom layer. The depleted sidewall layer is one of amorphous silicon or polycrystalline silicon. The method further forms an offset spacer layer over the depleted sidewall layer and over exposed surfaces of the bottom layer. | 01-14-2010 |
20100032759 | SELF-ALIGNED SOI SCHOTTKY BODY TIE EMPLOYING SIDEWALL SILICIDATION - A self-aligned Silicon on Insulator (SOI) Schottky Body Tie structure includes: a source region comprising a silicide layer disposed on a top surface of the source region; a drain region comprising a silicide layer disposed on a top surface of the drain region; a gate region disposed above a channel formed by the drain and source regions; and a gate oxide layer disposed between the gate region and the channel formed by the drain and source regions, wherein when silicidation is performed on the diffusion region it forms a metal-silicon alloy contact such that the silicide layer extends into and directly touches the channel. | 02-11-2010 |
20100038715 | THIN BODY SILICON-ON-INSULATOR TRANSISTOR WITH BORDERLESS SELF-ALIGNED CONTACTS - A method for fabricating a thin-silicon-on-insulator transistor with borderless self-aligned contacts is disclosed. A gate stack is formed on a silicon layer that is above a buried oxide layer. The gate stack includes a gate oxide layer on the silicon layer and a gate electrode layer on the gate oxide layer. A hard mask on top of the gate stack is formed. An off-set spacer is formed surrounding the gate stack. A raised source/drain region is epitaxially formed adjacent to the off-set spacer. The raised source/drain region is grown slightly about a height of the gate stack including the hard mask. The raised source/drain region forms borderless self-aligned contact. | 02-18-2010 |
20100038723 | SELF-ALIGNED BORDERLESS CONTACTS FOR HIGH DENSITY ELECTRONIC AND MEMORY DEVICE INTEGRATION - A method for fabricating a transistor having self-aligned borderless electrical contacts is disclosed. A gate stack is formed on a silicon region. An off-set spacer is formed surrounding the gate stack. A sacrificial layer that includes a carbon-based film is deposited overlying the silicon region, the gate stack, and the off-set spacer. A pattern is defined in the sacrificial layer to define a contact area for the electrical contact. The pattern exposes at least a portion of the gate stack and source/drain. A dielectric layer is deposited overlying the sacrificial layer that has been patterned and the portion of the gate stack that has been exposed. The sacrificial layer that has been patterned is selectively removed to define the contact area at the height that has been defined. The contact area for the height that has been defined is metalized to form the electrical contact. | 02-18-2010 |
20110049626 | ASYMMETRIC EMBEDDED SILICON GERMANIUM FIELD EFFECT TRANSISTOR - A semiconductor device, an integrated circuit, and method for fabricating the same are disclosed. The semiconductor device includes a gate stack formed on an active region of a silicon-on-insulator substrate. A gate spacer is formed over the gate stack. A source region that includes embedded silicon germanium is formed within the semiconductor layer. A drain region that includes embedded silicon germanium is formed within the semiconductor layer. The source region includes an angled implantation region that extends into the embedded silicon germanium of the source region, and is asymmetric relative to the drain region. | 03-03-2011 |
20110049627 | EMBEDDED SILICON GERMANIUM N-TYPE FILED EFFECT TRANSISTOR FOR REDUCED FLOATING BODY EFFECT - A method for fabricating a semiconductor device includes forming a gate stack on an active region of a silicon-on-insulator substrate. The active region is within a semiconductor layer and is doped with an p-type dopant. A gate spacer is formed surrounding the gate stack. A first trench is formed in a region reserved for a source region and a second trench is formed in a region reserved for a drain region. The first and second trenches are formed while maintaining exposed the region reserved for the source region and the region reserved for the drain region. Silicon germanium is epitaxially grown within the first trench and the second trench while maintaining exposed the regions reserved for the source and drain regions, respectively. | 03-03-2011 |
20110241073 | STRUCTURE FOR SELF-ALIGNED SILICIDE CONTACTS TO AN UPSIDE-DOWN FET BY EPITAXIAL SOURCE AND DRAIN - A method for fabricating an upside-down p-FET includes: fully etching source and drain regions in a donor substrate by etching a silicon-on-insulator layer through buried oxide and partially etching the silicon substrate; refilling a bottom and sidewall surfaces of the etched source and drain regions with epitaxial silicide/germanide to form e-SiGe source and drain regions; capping the source and drain regions with self-aligning silicide/germanide; providing a silicide layer formed over the gate conductor line; providing a first stress liner over the gate and the e-SiGe source and drain regions; depositing a planarized dielectric over the self-aligning silicide/germanide; inverting the donor substrate; bonding the donor substrate to a host wafer; and selectively exposing the buried oxide and the e-SiGe source and drain regions by removing the donor wafer. | 10-06-2011 |
20110254080 | TUNNEL FIELD EFFECT TRANSISTOR - A method for fabricating an FET device characterized as being a tunnel FET (TFET) device is disclosed. The method includes processing a gate-stack, and processing the adjoining source and drain junctions, which are of a first conductivity type. A hardmask is formed covering the gate-stack and the junctions. A tilted angle ion implantation is performed which is received by a first portion of the hardmask, and it is not received by a second portion of the hardmask due to the shadowing of the gate-stack. The implanted portion of the hardmask is removed and one of the junctions is exposed. The junction is etched away, and a new junction, typically in-situ doped to a second conductivity type, is epitaxially grown into its place. A device characterized as being an asymmetrical TFET is also disclosed. The source and drain junctions of the TFET are of different conductivity types, and the TFET also includes spacer formations in a manner that the spacer formation on one side of the gate-stack is thinner than on the other side of the gate-stack. | 10-20-2011 |
20120138900 | Omega Shaped Nanowire Tunnel Field Effect Transistors - A method for forming a nanowire tunnel field effect transistor device includes forming a nanowire connected to a first pad region and a second pad region, the nanowire including a core portion and a dielectric layer, forming a gate structure on the dielectric layer of the nanowire, forming a first protective spacer on portions of the nanowire, implanting ions in a first portion of the exposed nanowire and the first pad region, implanting in the dielectric layer of a second portion of the exposed nanowire and the second pad region, removing the dielectric layer from the second pad region and the second portion, removing the core portion of the second portion of the exposed nanowire to form a cavity, and epitaxially growing a doped semiconductor material in the cavity to connect the exposed cross sections of the nanowire to the second pad region. | 06-07-2012 |
20120175678 | REPLACEMENT SPACER FOR TUNNEL FETS - A semiconductor fabrication method includes depositing a dummy gate layer onto a substrate, patterning the dummy gate layer, depositing a hardmask layer over the dummy gate layer, patterning the hardmask layer, etching a recess into the substrate, adjacent the dummy gate layer, depositing a semiconductor material into the recess, removing the hardmask layer, depositing replacement spacers onto the dummy gate layer, performing an oxide deposition over the dummy gate layer and replacement spacers, removing the dummy gate and replacement spacers, thereby forming a gate recess in the oxide and depositing a gate stack into the recess. | 07-12-2012 |
20120286350 | TUNNEL FIELD EFFECT TRANSISTOR - An FET device characterized as being an asymmetrical tunnel FET (TFET) is disclosed. The TFET includes a gate-stack, a channel region underneath the gate-stack, a first and a second junction adjoining the gate-stack and being capable for electrical continuity with the channel. The first junction and the second junction are of different conductivity types. The TFET also includes spacer formations in a manner that the spacer formation on one side of the gate-stack is thinner than on the other side. | 11-15-2012 |
20120289014 | METHOD FOR FABRICATING TRANSISTOR WITH HIGH-K DIELECTRIC SIDEWALL SPACER - A method is provided for fabricating a transistor. The transistor includes a silicon layer including a source region and a drain region, a gate stack disposed on the silicon layer between the source region and the drain region, and a sidewall spacer disposed on sidewalls of the gate stack. The gate stack includes a first layer of high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. The sidewall spacer includes a high dielectric constant material and covers the sidewalls of at least the second and third layers of the gate stack. Also provided is a method for fabricating such a transistor. | 11-15-2012 |
20120299062 | EMBEDDED SILICON GERMANIUM N-TYPE FILED EFFECT TRANSISTOR FOR REDUCED FLOATING BODY EFFECT - A method for fabricating a semiconductor device includes forming a gate stack on an active region of a silicon-on-insulator substrate. The active region is within a semiconductor layer and is doped with an p-type dopant. A gate spacer is formed surrounding the gate stack. A first trench is formed in a region reserved for a source region and a second trench is formed in a region reserved for a drain region. The first and second trenches are formed while maintaining exposed the region reserved for the source region and the region reserved for the drain region. Silicon germanium is epitaxially grown within the first trench and the second trench while maintaining exposed the regions reserved for the source and drain regions, respectively. | 11-29-2012 |
20120299101 | THIN BODY SILICON-ON-INSULATOR TRANSISTOR WITH BORDERLESS SELF-ALIGNED CONTACTS - A thin-silicon-on-insulator transistor with borderless self-aligned contacts includes a buried oxide layer above a substrate. A silicon layer overlays the buried oxide layer. A gate stack is on the silicon layer. The gate stack includes a gate oxide layer on the silicon layer and a gate electrode on the gate oxide layer. An off-set spacer surrounds the gate stack. Raised source/drain regions each have a first part overlying a portion of the silicon layer, a second part adjacent to off-set spacer, and a third part extending about a top portion of the gate stack. | 11-29-2012 |
20120313174 | METHOD OF MAKING A MOSFET HAVING SELF-ALIGNED SILICIDED SCHOTTKY BODY TIE INCLUDING INTENTIONAL PULL-DOWN OF AN STI EXPOSING SIDEWALLS OF A DIFFUSION REGION - A self-aligned transistor device includes: a source region and drain regions disposed on an oxide layer; a channel with a diffusion region formed between the drain and source regions; a silicide layer over a top surface of the source and drain regions, extending into the diffusion region; and a recess formed on each end of the device to expose sidewalls of the device to a free surface by performing shallow trench isolation on the oxide layer of the device that extends past the silicide layer. | 12-13-2012 |
20140035037 | EMBEDDED SILICON GERMANIUM N-TYPE FILED EFFECT TRANSISTOR FOR REDUCED FLOATING BODY EFFECT - A semiconductor device includes a gate stack formed on an active region in a p-type field effect transistor (pFET) portion of a silicon-on-insulator (SOI) substrate. The SOI substrate includes a n-type field effect transistor (nFET) portion. A gate spacer is formed over the gate stack. A source region and a drain region are formed within a first region and a second region, respectively, of the pFET portion of the semiconductor layer including embedded silicon germanium (eSiGe). A source region and a drain region are formed within a first region and a second region, respectively, of the nFET portion of the semiconductor layer including eSiGe. The source and drain regions within the pFET portion includes at least one dimension that is different from at least one dimension of the source and drain regions within the nFET portion. | 02-06-2014 |
20140038368 | EMBEDDED SILICON GERMANIUM N-TYPE FILED EFFECT TRANSISTOR FOR REDUCED FLOATING BODY EFFECT - A method for fabricating a semiconductor device includes forming a gate stack on an active region of a silicon-on-insulator substrate. The active region is within a semiconductor layer and is doped with an p-type dopant. A gate spacer is formed surrounding the gate stack. A first trench is formed in a region reserved for a source region and a second trench is formed in a region reserved for a drain region. The first and second trenches are formed while maintaining exposed the region reserved for the source region and the region reserved for the drain region. Silicon germanium is epitaxially grown within the first trench and the second trench while maintaining exposed the regions reserved for the source and drain regions, respectively. | 02-06-2014 |
20140183637 | STRUCTURE FOR SELF-ALIGNED SILICIDE CONTACTS TO AN UPSIDE-DOWN FET BY EPITAXIAL SOURCE AND DRAIN - An upside-down p-FET is provided on a donor substrate. The upside-down p-FET includes: self-terminating e-SiGe source and drain regions; a cap of self-aligning silicide/germanide over the e-SiGe source and drain regions; a silicon channel region connecting the e-SiGe source and drain regions; buried oxide above the silicon channel region; and a gate controlling current flow from the e-SiGe source region to the e-SiGe drain region. | 07-03-2014 |