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Isaac, CA
Charles Isaac, Carlsbad, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080317731 | Phospholipases, Nucleic Acids Encoding Them and Methods for Making and Using Them - The invention provides novel polypeptides having phospholipase activity, including, e.g., phospholipase A, B, C and D activity, patatin activity, phosphatidic acid phosphatases (PAP)) and/or lipid acyl hydrolase (LAH) activity, nucleic acids encoding them and antibodies that bind to them. Industrial methods, e.g., oil degumming, and products comprising use of these phospholipases are also provided. | 12-25-2008 |
| 20090053191 | PHOSPHOLIPASES, NUCLEIC ACIDS ENCODING THEM AND METHODS FOR MAKING AND USING THEM - The invention provides novel polypeptides having phospholipase activity, including, e.g., phospholipase A, B, C and D activity, patatin activity, lipid acyl hydrolase (LAH) activity, nucleic acids encoding them and antibodies that bind to them. Industrial methods, e.g., oil degumming, and products comprising use of these phospholipases are also provided. | 02-26-2009 |
George I. Isaac, Port Hueneme, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110112599 | MRI SIGNAL FILTERING FOR IMPLANTABLE MEDICAL DEVICE - A filtering scheme for an implantable medical device mitigates potentially adverse effects that may be caused by MRI-induced signals. In some aspects filtering is provided to attenuate MRI-induced signals on an implanted cardiac lead that is coupled to an implanted device. In some aspects the filter may be configured to complement a capacitor circuit (e.g., a feedthrough capacitor) that reduces the amount of EMI that enters the implanted device via the cardiac lead. In some implementations the filter consists of a LC tank circuit and a series LC circuit, where the LC tank circuit is in series with the cardiac lead and a cardiac stimulation circuit and the series LC circuit is in a shunt configuration across the cardiac stimulation circuit. | 05-12-2011 |
| 20110245888 | MEDICAL DEVICE WITH CHARGE LEAKAGE DETECTION - A medical device (implantable or external) is provided that comprises a power source, a charge storage member, a terminal connector, a switch network, a controller and a leak detection module. The charge storage member is configured to receive and store energy from the power source. The terminal connector is configured to be coupled to a lead to be implanted in a patient proximate to tissue of interest. The switch network is electrically disposed between the charge storage member and the terminal connector. The switch network changes between open and closed states to disconnect and connect the charge storage member and the terminal connector. The controller controls storage of energy in the charge storage member and delivery of stimulating pulses from the charge storage member to the lead coupled to the terminal connector. The leak detection module obtains a leakage measurement by sensing at least one of i) a voltage potential of the charge storage member and ii) current flow from the charge storage member. The leak detection module compares the leakage measurement to a leakage threshold to determine when the leakage measurement satisfies the leakage threshold. | 10-06-2011 |
Gregory J. Isaac, Coto De Caza, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100210435 | ADAPTABLE FOAM ROLLER - A composite paint roller is provided for improving ease of cleaning, manufacture and adaptability of the same. The roller comprises an elongate cylindrical core, a sheath, and first and second end caps. The sheath is removably mountable about and frictionally engageable to the core. The core defines a core length and opposing open ends. The sheath defines an axial length and opposing sheath ends. The axial length of the sheath is greater than the core length with the opposing sheath ends being foldable and axially insertable into the opposing open ends to produce a radial compression of the sheath adjacent the opposing open ends. The radial compression creates opposing beveled ends of the roller. The first and second end caps each are attachable to the opposing open ends to secure the opposing sheath ends within the opposing open ends. | 08-19-2010 |
Hadar Isaac, Los Altos, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100153017 | Methods and Workflows for Selecting Genetic Markers Utilizing Software Tool - A visual tool facilitates selecting SNPs for genotyping experiments comprises a first memory containing a datastore of pre-calculated linkage disequilibrium map information; a second memory containing a datastore of haplotype block information; and a third memory containing at least one set of tagging SNPs. A graphical user interface provides visualization of SNPs, integrated with a physical genome map. A stepwise selection tool associated with the graphical user interface facilitates selection of tagging SNPs by selectively using the information in at least one of the first, second and third memories. | 06-17-2010 |
Leroy Kevin Isaac, San Francisco, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090200385 | FINANCIAL TRANSACTION CARD WITH NON-EMBOSSED, RAISED INDICIA - A financial transaction card has a first major surface on one side and a second major surface on an opposite side. A first set of raised indicia projects outwardly from the first major surface. A second set of raised indicia projects outwardly from the second major surface and is directly contralateral with the first set of raised indicia. The second major surface is devoid of any indication of the first set of raised indicia and the first major surface is devoid of any indication of the second set of raised indicia. Each indicium denotes an alphabetic letter or a number and in one embodiment is a Braille character. | 08-13-2009 |
Roger Isaac, Santa Clara, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090049256 | MEMORY CONTROLLER PRIORITIZATION SCHEME - A system includes a processor coupled to a memory through a memory controller. The memory controller includes first and second queues. The memory controller receives memory requests from the processor, assigns a priority to each request, stores each request in the first queue, and schedules processing of the requests based on their priorities. The memory controller changes the priority of a request in the first queue in response to a trigger, sends a next scheduled request from the first queue to the second queue in response to detecting the next scheduled request has the highest priority of any request in the first queue, and sends requests from the second queue to the memory. The memory controller changes the priority of different types of requests in response to different types of triggers. The memory controller maintains a copy of each request sent to the second queue in the first queue. | 02-19-2009 |
Roger D. Isaac, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110196997 | HYBRID INTERFACE FOR SERIAL AND PARALLEL COMMUNICATION - Embodiments of the invention are generally directed to a hybrid interface for serial and parallel communication. An embodiment of a method includes initializing a first apparatus for transmission of data to or reception of data from a second apparatus, switching an interface for the first apparatus to a first mode for a parallel interface, the parallel interface including a first plurality of pins, and transmitting or receiving parallel data in the first mode via the first plurality of pins. The method further includes switching the interface of the first apparatus to a second mode for a serial interface, the serial interface including a second plurality of pins, the first plurality of pins and the second plurality of pins both including an overlapping set of pins, and transmitting or receiving serial data in the second mode via the second plurality of pins. | 08-11-2011 |
Roger Dwain Isaac, Santa Clara, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090132736 | MEMORY BUFFERING SYSTEM THAT IMPROVES READ/WRITE PERFORMANCE AND PROVIDES LOW LATENCY FOR MOBILE SYSTEMS - A memory buffering system is disclosed that arbitrates bus ownership through all arbitration scheme for memory elements in chain architecture. A unified host memory controller arbitrates bus ownership for transfer to a unified memory buffer and other buffers within the chain architecture. The system is used within a communication system with a bus in chain architectures and parallel architectures. | 05-21-2009 |
| 20100281293 | REPLACING RESET PIN IN BUSES WHILE GUARANTEEING SYSTEM RECOVERY - Systems and methods are disclosed that replace a separate reset pin in a bus with a reset command that guarantees a system recovery. The system comprises a host component circuitry residing on a first chip and a client component circuitry residing on a second, different chip. A bus connects the host component circuitry to the client component circuitry. The host component circuitry is configured to transfer an initial client value associated with a client component time period to the client component circuitry over the bus on a periodic time basis. The periodic time basis is dictated by a host component time period and the client component time period is greater than the host component time period. The client component circuitry is configured to initiate a reset procedure if the client component time period expires which indicates that the initial client value was not received at a next time on the periodic time basis dictated by the host component time period. | 11-04-2010 |
Roger Dwain Isaac, Campbell, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090109769 | SIGNAL DESCRAMBLING DETECTOR - Systems and/or methods that facilitate descrambling of data communicated between a memory and a host processor are presented. A descrambler component determines the bit order of data signals from a memory device based on pattern information provided to the descrambler component by the memory device during initialization. The descrambler component can receive one or more distinct patterns and can evaluate the data values associated with such patterns for each data line of the memory. The descrambler component can determine the bit order of the data signals based on such patterns and can generate a transformation function that can facilitate rearranging data, which can be received from or sent to the memory device, into a predetermined bit order. | 04-30-2009 |
| 20090138570 | METHOD FOR SETTING PARAMETERS AND DETERMINING LATENCY IN A CHAINED DEVICE SYSTEM - A storage system and method for setting parameters and determining latency in a chained device system. Storage nodes store information and the storage nodes are organized in a daisy chained network. At least one of one of the storage nodes includes an upstream communication buffer. Flow of information to the storage nodes is based upon constraints of the communication buffer within the storage nodes. In one embodiment, communication between the master controller and the plurality storage nodes has a determined maximum latency. | 05-28-2009 |
| 20090138597 | SYSTEM AND METHOD FOR ACCESSING MEMORY - A storage system and method for storing information in memory nodes. The storage or memory nodes include a communication buffer. Flow of information to the storage nodes is controlled based upon constraints on the communication buffer. In one embodiment, communications between a master controller and a storage node have a determined maximum latency. | 05-28-2009 |
| 20090138624 | STORAGE SYSTEM AND METHOD - Efficient and convenient storage systems and methods are presented. In one embodiment a storage system includes a plurality of storage nodes and a master controller. The storage nodes store information. The storage node includes an upstream communication buffer which is locally controlled at the storage node to facilitate resolution of conflicts in upstream communications. The master controller controlls the flow of traffic to the node based upon constraints of the upstream communication buffer. In one embodiment, communication between the master controller and the node has a determined maximum latency. The storage node can be coupled to the master controller in accordance with a chain memory configuration. | 05-28-2009 |
Ronald Nadim Isaac, San Jose, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20120082317 | ELECTRONIC DEVICES WITH IMPROVED AUDIO - An electronic device having an enclosure including an upper panel and a bottom panel operably connected to the upper panel. A transducer is operably connected to the enclosure and the transducer is configured to mechanically vibrate the enclosure. The transducer includes an electromagnet, a magnet in communication with the electromagnet and a bracket substantially surrounding the electromagnet and the magnet, the bracket substantially secures the transducer to the bottom panel. | 04-05-2012 |
Timothy Reynard Isaac, Brea, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100274673 | Non-Intrusive Media Linked and Embedded Information Delivery - A method for information delivery is disclosed. The method includes directing the display of a multimedia presentation in a first screen segment. The multimedia presentation is associated with a reference tag descriptive of an aspect thereof. An information link corresponding to the reference tag in a second screen segment is generated. The information link is contextually related to the multimedia presentation in accordance with the reference tag. Thereafter, a selection input of the information link is received from one of the viewers while mitigating obstruction of the displaying of the multimedia presentation. The selected information link and the identity of the viewer are associated as a marker. | 10-28-2010 |